📄 sead.h
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/******** reg: SD_TREFRESH ********/#define SEAD_SD_TREFRESH_TREF_SHF 0#define SEAD_SD_TREFRESH_TREF_MSK (MSK(11) << SEAD_SD_TREFRESH_TREF_SHF)/******** reg: SD_SPDCNF ********/#define SEAD_SD_SPDCNF_CPDIV_SHF 0#define SEAD_SD_SPDCNF_CPDIV_MSK (MSK(10) << SEAD_SD_SPDCNF_CPDIV_SHF)/******** reg: SD_SPDADR ********/#define SEAD_SD_SPDADR_RDADR_SHF 0#define SEAD_SD_SPDADR_RDADR_MSK (MSK(8) << SEAD_SD_SPDADR_RDADR_SHF)/******** reg: SD_SPDDAT ********/#define SEAD_SD_SPDDAT_READ_ERR_SHF 9#define SEAD_SD_SPDDAT_READ_ERR_MSK (MSK(1) << SEAD_SD_SPDDAT_READ_ERR_SHF)#define SEAD_SD_SPDDAT_READ_ERR_BIT SEAD_SD_SPDDAT_READ_ERR_MSK#define SEAD_SD_SPDDAT_BUSY_SHF 8#define SEAD_SD_SPDDAT_BUSY_MSK (MSK(1) << SEAD_SD_SPDDAT_BUSY_SHF)#define SEAD_SD_SPDDAT_BUSY_BIT SEAD_SD_SPDDAT_BUSY_MSK#define SEAD_SD_SPDDAT_RDATA_SHF 0#define SEAD_SD_SPDDAT_RDATA_MSK (MSK(8) << SEAD_SD_SPDDAT_RDATA_SHF)/************************************************************************ ************************************************************************ * SEAD FPGA, GENERAL PURPOSE INPUT/OUTPUT REGISTERS: ************************************************************************ ************************************************************************//************************************************************************ * Register Addresses*************************************************************************/#define SEAD_GP_DIRRAWB0 (SEAD_GP_BASE + 0x00C0)#define SEAD_GP_DIRRAWB1 (SEAD_GP_BASE + 0x00C8)#define SEAD_GP_DIRRAWA0 (SEAD_GP_BASE + 0x00D0)#define SEAD_GP_DIRRAWA1 (SEAD_GP_BASE + 0x00D8)#define SEAD_GP_INB0 (SEAD_GP_BASE + 0x0100)#define SEAD_GP_INB1 (SEAD_GP_BASE + 0x0108)#define SEAD_GP_INA0 (SEAD_GP_BASE + 0x0110)#define SEAD_GP_INA1 (SEAD_GP_BASE + 0x0118)#define SEAD_GP_OUTRAWB0 (SEAD_GP_BASE + 0x01C0)#define SEAD_GP_OUTRAWB1 (SEAD_GP_BASE + 0x01C8)#define SEAD_GP_OUTRAWA0 (SEAD_GP_BASE + 0x01D0)#define SEAD_GP_OUTRAWA1 (SEAD_GP_BASE + 0x01D8)#define SEAD_GP_DIRINB0 (SEAD_GP_BASE + 0x0040)#define SEAD_GP_DIRINB1 (SEAD_GP_BASE + 0x0048)#define SEAD_GP_DIRINA0 (SEAD_GP_BASE + 0x0050)#define SEAD_GP_DIRINA1 (SEAD_GP_BASE + 0x0058)#define SEAD_GP_DIROUTB0 (SEAD_GP_BASE + 0x0080)#define SEAD_GP_DIROUTB1 (SEAD_GP_BASE + 0x0088)#define SEAD_GP_DIROUTA0 (SEAD_GP_BASE + 0x0090)#define SEAD_GP_DIROUTA1 (SEAD_GP_BASE + 0x0098)#define SEAD_GP_OUTSETB0 (SEAD_GP_BASE + 0x0140)#define SEAD_GP_OUTSETB1 (SEAD_GP_BASE + 0x0148)#define SEAD_GP_OUTSETA0 (SEAD_GP_BASE + 0x0150)#define SEAD_GP_OUTSETA1 (SEAD_GP_BASE + 0x0158)#define SEAD_GP_OUTCLRB0 (SEAD_GP_BASE + 0x0180)#define SEAD_GP_OUTCLRB1 (SEAD_GP_BASE + 0x0188)#define SEAD_GP_OUTCLRA0 (SEAD_GP_BASE + 0x0190)#define SEAD_GP_OUTCLRA1 (SEAD_GP_BASE + 0x0198)/************************************************************************ * Register field encodings*************************************************************************//* 1 bit per pin. * "B0" controls UC_B[31:0] * "B1" controls UC_B[63:32] * "A0" controls UC_A[31:0] * "A1" controls UC_A[39:32] *//************************************************************************ ************************************************************************ * SEAD FPGA, PERFORMANCE & F-SW/F-LED MODULE REGISTERS: ************************************************************************ ************************************************************************//************************************************************************ * Register Addresses*************************************************************************/#define SEAD_PF_MODE (SEAD_PF_BASE + 0x0000)#define SEAD_PF_FSWITCH (SEAD_PF_BASE + 0x0020)#define SEAD_PF_FLED (SEAD_PF_BASE + 0x0040)#define SEAD_PF_SPEED (SEAD_PF_BASE + 0x0060)/************************************************************************ * Register field encodings*************************************************************************//******** reg: PF_MODE ********/#define SEAD_PF_MODE_FORCE_SHF 0#define SEAD_PF_MODE_FORCE_MSK (MSK(1) << SEAD_PF_MODE_FORCE_SHF)#define SEAD_PF_MODE_FORCE_BIT SEAD_PF_MODE_FORCE_MSK#define SEAD_PF_MODE_MVAL_SHF 1#define SEAD_PF_MODE_MVAL_MSK (MSK(3) << SEAD_PF_MODE_MVAL_SHF)#define SEAD_PF_MODE_MVAL_SPEED 0 /* speed-o-meter mode */#define SEAD_PF_MODE_MVAL_HTMSS 1 /* hit/miss mode */#define SEAD_PF_MODE_MVAL_SIHT 2 /* sysint/hit mode */#define SEAD_PF_MODE_MVAL_CCHIC 3 /* cache/instcompl mode */#define SEAD_PF_MODE_MVAL_FLED 7 /* PF_FLED mode *//******** reg: PF_FSWITCH ********//* bits 7:0: VAL */#define SEAD_PF_FSWITCH_VAL_SHF 0#define SEAD_PF_FSWITCH_VAL_MSK (MSK(8) << SEAD_PF_FSWITCH_VAL_SHF)/* bit 0: S5-1 */#define SEAD_PF_FSWITCH_SW1_SHF 0#define SEAD_PF_FSWITCH_SW1_MSK (MSK(1) << SEAD_PF_FSWITCH_SW1_SHF)#define SEAD_PF_FSWITCH_SW1_ON SEAD_PF_FSWITCH_SW1_MSK/* bit 1: S5-2 */#define SEAD_PF_FSWITCH_SW2_SHF 1#define SEAD_PF_FSWITCH_SW2_MSK (MSK(1) << SEAD_PF_FSWITCH_SW2_SHF)#define SEAD_PF_FSWITCH_SW2_ON SEAD_PF_FSWITCH_SW2_MSK/* bit 2: S5-3 */#define SEAD_PF_FSWITCH_SW3_SHF 2#define SEAD_PF_FSWITCH_SW3_MSK (MSK(1) << SEAD_PF_FSWITCH_SW3_SHF)#define SEAD_PF_FSWITCH_SW3_ON SEAD_PF_FSWITCH_SW3_MSK/* bit 3: S5-4 */#define SEAD_PF_FSWITCH_SW4_SHF 3#define SEAD_PF_FSWITCH_SW4_MSK (MSK(1) << SEAD_PF_FSWITCH_SW4_SHF)#define SEAD_PF_FSWITCH_SW4_ON SEAD_PF_FSWITCH_SW4_MSK/* bit 4: S5-5 */#define SEAD_PF_FSWITCH_SW5_SHF 4#define SEAD_PF_FSWITCH_SW5_MSK (MSK(1) << SEAD_PF_FSWITCH_SW5_SHF)#define SEAD_PF_FSWITCH_SW5_ON SEAD_PF_FSWITCH_SW5_MSK/* bit 5: S5-6 */#define SEAD_PF_FSWITCH_SW6_SHF 5#define SEAD_PF_FSWITCH_SW6_MSK (MSK(1) << SEAD_PF_FSWITCH_SW6_SHF)#define SEAD_PF_FSWITCH_SW6_ON SEAD_PF_FSWITCH_SW6_MSK/* bit 6: S5-7 */#define SEAD_PF_FSWITCH_SW7_SHF 6#define SEAD_PF_FSWITCH_SW7_MSK (MSK(1) << SEAD_PF_FSWITCH_SW7_SHF)#define SEAD_PF_FSWITCH_SW7_ON SEAD_PF_FSWITCH_SW7_MSK/* bit 7: S5-8 */#define SEAD_PF_FSWITCH_SW8_SHF 7#define SEAD_PF_FSWITCH_SW8_MSK (MSK(1) << SEAD_PF_FSWITCH_SW8_SHF)#define SEAD_PF_FSWITCH_SW8_ON SEAD_PF_FSWITCH_SW8_MSK/******** reg: PF_FLED ********//* bits 7:0: VAL */#define SEAD_PF_FLED_VAL_SHF 0#define SEAD_PF_FLED_VAL_MSK (MSK(8) << SEAD_PF_FLED_VAL_SHF)/* bit 0: */#define SEAD_PF_FLED_BIT0_SHF 0#define SEAD_PF_FLED_BIT0_MSK (MSK(1) << SEAD_PF_FLED_BIT0_SHF)#define SEAD_PF_FLED_BIT0_ON SEAD_PF_FLED_BIT0_MSK/* bit 1: */#define SEAD_PF_FLED_BIT1_SHF 1#define SEAD_PF_FLED_BIT1_MSK (MSK(1) << SEAD_PF_FLED_BIT1_SHF)#define SEAD_PF_FLED_BIT1_ON SEAD_PF_FLED_BIT1_MSK/* bit 2: */#define SEAD_PF_FLED_BIT2_SHF 2#define SEAD_PF_FLED_BIT2_MSK (MSK(1) << SEAD_PF_FLED_BIT2_SHF)#define SEAD_PF_FLED_BIT2_ON SEAD_PF_FLED_BIT2_MSK/* bit 3: */#define SEAD_PF_FLED_BIT3_SHF 3#define SEAD_PF_FLED_BIT3_MSK (MSK(1) << SEAD_PF_FLED_BIT3_SHF)#define SEAD_PF_FLED_BIT3_ON SEAD_PF_FLED_BIT3_MSK/* bit 4: */#define SEAD_PF_FLED_BIT4_SHF 4#define SEAD_PF_FLED_BIT4_MSK (MSK(1) << SEAD_PF_FLED_BIT4_SHF)#define SEAD_PF_FLED_BIT4_ON SEAD_PF_FLED_BIT4_MSK/* bit 5: */#define SEAD_PF_FLED_BIT5_SHF 5#define SEAD_PF_FLED_BIT5_MSK (MSK(1) << SEAD_PF_FLED_BIT5_SHF)#define SEAD_PF_FLED_BIT5_ON SEAD_PF_FLED_BIT5_MSK/* bit 6: */#define SEAD_PF_FLED_BIT6_SHF 6#define SEAD_PF_FLED_BIT6_MSK (MSK(1) << SEAD_PF_FLED_BIT6_SHF)#define SEAD_PF_FLED_BIT6_ON SEAD_PF_FLED_BIT6_MSK/* bit 7: */#define SEAD_PF_FLED_BIT7_SHF 7#define SEAD_PF_FLED_BIT7_MSK (MSK(1) << SEAD_PF_FLED_BIT7_SHF)#define SEAD_PF_FLED_BIT7_ON SEAD_PF_FLED_BIT7_MSK/******** reg: PF_SPEED ********/#define SEAD_PF_SPEED_VAL_SHF 0#define SEAD_PF_SPEED_VAL_MSK (MSK(8) << SEAD_PF_SPEED_VAL_SHF)/************************************************************************ ************************************************************************ * Physical address setup for sead2_msc01 ************************************************************************ ************************************************************************/#define SEAD_MSC01_MEMORY_BASE SEAD_SYSTEMRAM_BASE /* MEM */#define SEAD_MSC01_MEMORY_SIZE SEAD_SYSTEMRAM_SIZE#define SEAD_MSC01_IP2MEM_BASE 0x1b400000 /* IP2 (unused) must point somewhere */#define SEAD_MSC01_IP2MEM_SIZE 0x00400000#define SEAD_MSC01_IP1MEM_BASE 0x1b800000 /* IP1 (unused) must point somewhere */#define SEAD_MSC01_IP1MEM_SIZE 0x00400000 #define SEAD_MSC01_REG_BASE 0x1bc00000#define SEAD_MSC01_REG_SIZE 0x00400000#define SEAD_MSC01_PBCMEM_BASE 0x1c000000 /* IP3 */#define SEAD_MSC01_PBCMEM_SIZE 0x04000000#define SEAD_MSC01_IP3MEM_SIZE 0x00400000 /* temporary size during start up *//**** IRQ definitions for SEAD MSC01 devices ****/#define SEAD_MSC01_INTLINE_COUNTER 0#define SEAD_MSC01_INTLINE_TTY0 2#define SEAD_MSC01_INTLINE_TTY1 3#define SEAD_MSC01_IC_COUNT 4#define SEAD_MSC01_CPUINT (S_StatusIM2 - S_StatusIM)/**** SW reset definitions for SEAD MSC01 devices ****/#define SEAD2_MSC01_MC_RESET_SHF 15#define SEAD2_MSC01_MC_RESET_MSK (MSK(1) << SEAD2_MSC01_MC_RESET_SHF)#define SEAD2_MSC01_MC_RESET_BIT SEAD2_MSC01_MC_RESET_MSK/************************************************************************ ************************************************************************ * MISC definitions ************************************************************************ ************************************************************************//* * SEAD temporary hack to set the processor clock for further * calculations */#define SEAD_MIN_FREQ_MHZ 2#define SEAD_MAX_FREQ_MHZ 25#endif /* #ifndef SEAD_H */⌨️ 快捷键说明
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