sead.h

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: PLED ********/
/* bits 7:0: VAL */
#define SEAD_PLED_VAL_SHF	    	0
#define SEAD_PLED_VAL_MSK	    	(MSK(8) << SEAD_PLED_VAL_SHF)


/* bit 0:  */
#define SEAD_PLED_BIT0_SHF	    	0
#define SEAD_PLED_BIT0_MSK	    	(MSK(1) << SEAD_PLED_BIT0_SHF)
#define SEAD_PLED_BIT0_ON           	SEAD_PLED_BIT0_MSK

/* bit 1:  */
#define SEAD_PLED_BIT1_SHF	    	1
#define SEAD_PLED_BIT1_MSK	    	(MSK(1) << SEAD_PLED_BIT1_SHF)
#define SEAD_PLED_BIT1_ON           	SEAD_PLED_BIT1_MSK

/* bit 2:  */
#define SEAD_PLED_BIT2_SHF	    	2
#define SEAD_PLED_BIT2_MSK	    	(MSK(1) << SEAD_PLED_BIT2_SHF)
#define SEAD_PLED_BIT2_ON           	SEAD_PLED_BIT2_MSK

/* bit 3:  */
#define SEAD_PLED_BIT3_SHF	    	3
#define SEAD_PLED_BIT3_MSK	    	(MSK(1) << SEAD_PLED_BIT3_SHF)
#define SEAD_PLED_BIT3_ON           	SEAD_PLED_BIT3_MSK

/* bit 4:  */
#define SEAD_PLED_BIT4_SHF	    	4
#define SEAD_PLED_BIT4_MSK	    	(MSK(1) << SEAD_PLED_BIT4_SHF)
#define SEAD_PLED_BIT4_ON           	SEAD_PLED_BIT4_MSK

/* bit 5:  */
#define SEAD_PLED_BIT5_SHF	    	5
#define SEAD_PLED_BIT5_MSK	    	(MSK(1) << SEAD_PLED_BIT5_SHF)
#define SEAD_PLED_BIT5_ON           	SEAD_PLED_BIT5_MSK

/* bit 6:  */
#define SEAD_PLED_BIT6_SHF	    	6
#define SEAD_PLED_BIT6_MSK	    	(MSK(1) << SEAD_PLED_BIT6_SHF)
#define SEAD_PLED_BIT6_ON           	SEAD_PLED_BIT6_MSK

/* bit 7:  */
#define SEAD_PLED_BIT7_SHF	    	7
#define SEAD_PLED_BIT7_MSK	    	(MSK(1) << SEAD_PLED_BIT7_SHF)
#define SEAD_PLED_BIT7_ON           	SEAD_PLED_BIT7_MSK


/************************************************************************
 *  ASCII DISPLAY
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define SEAD_ASCIIPOS0          	0x1F0005C0
#define SEAD_ASCIIPOS1          	0x1F0005C8
#define SEAD_ASCIIPOS2          	0x1F0005D0
#define SEAD_ASCIIPOS3          	0x1F0005D8
#define SEAD_ASCIIPOS4          	0x1F0005E0
#define SEAD_ASCIIPOS5          	0x1F0005E8
#define SEAD_ASCIIPOS6          	0x1F0005F0
#define SEAD_ASCIIPOS7          	0x1F0005F8


/************************************************************************
 ************************************************************************
 *  SEAD FPGA, PERIPHERAL BUS CONTROLLER REGISTERS:
 ************************************************************************
 ************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define SEAD_PI_TIMSRAM             	(SEAD_PI_BASE + 0x0010)
#define SEAD_PI_TIMOTHER            	(SEAD_PI_BASE + 0x0020)


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: PI_TIMSRAM ********/

/* bit 2:0 : */
#define SEAD_PI_TIMSRAM_CS1_SHF		0
#define SEAD_PI_TIMSRAM_CS1_MSK		(MSK(3) << SEAD_PI_TIMSRAM_CS1_SHF)

/* bit 7:3 : */
#define SEAD_PI_TIMSRAM_CS2_SHF		3
#define SEAD_PI_TIMSRAM_CS2_MSK		(MSK(5) << SEAD_PI_TIMSRAM_CS2_SHF)

/* bit 10:8 : */
#define SEAD_PI_TIMSRAM_RD1_SHF		8
#define SEAD_PI_TIMSRAM_RD1_MSK		(MSK(3) << SEAD_PI_TIMSRAM_RD1_SHF)

/* bit 16:11 : */
#define SEAD_PI_TIMSRAM_RD2_SHF		11
#define SEAD_PI_TIMSRAM_RD2_MSK		(MSK(6) << SEAD_PI_TIMSRAM_RD2_SHF)

/* bit 19:17 : */
#define SEAD_PI_TIMSRAM_WE1_SHF		17
#define SEAD_PI_TIMSRAM_WE1_MSK		(MSK(3) << SEAD_PI_TIMSRAM_WE1_SHF)

/* bit 25:20 : */
#define SEAD_PI_TIMSRAM_WE2_SHF		20
#define SEAD_PI_TIMSRAM_WE2_MSK		(MSK(6) << SEAD_PI_TIMSRAM_WE2_SHF)

/* bit 31:26 : */
#define SEAD_PI_TIMSRAM_ADH_SHF		26
#define SEAD_PI_TIMSRAM_ADH_MSK		(MSK(6) << SEAD_PI_TIMSRAM_ADH_SHF)


/******** reg: PI_TIMOTHER ********/

/* bit 2:0 : */
#define SEAD_PI_TIMOTHER_CS1_SHF	0
#define SEAD_PI_TIMOTHER_CS1_MSK	(MSK(3) << SEAD_PI_TIMOTHER_CS1_SHF)

/* bit 7:3 : */
#define SEAD_PI_TIMOTHER_CS2_SHF	3
#define SEAD_PI_TIMOTHER_CS2_MSK	(MSK(5) << SEAD_PI_TIMOTHER_CS2_SHF)

/* bit 10:8 : */
#define SEAD_PI_TIMOTHER_RD1_SHF	8
#define SEAD_PI_TIMOTHER_RD1_MSK	(MSK(3) << SEAD_PI_TIMOTHER_RD1_SHF)

/* bit 16:11 : */
#define SEAD_PI_TIMOTHER_RD2_SHF	11
#define SEAD_PI_TIMOTHER_RD2_MSK	(MSK(6) << SEAD_PI_TIMOTHER_RD2_SHF)

/* bit 19:17 : */
#define SEAD_PI_TIMOTHER_WE1_SHF	17
#define SEAD_PI_TIMOTHER_WE1_MSK	(MSK(3) << SEAD_PI_TIMOTHER_WE1_SHF)

/* bit 25:20 : */
#define SEAD_PI_TIMOTHER_WE2_SHF	20
#define SEAD_PI_TIMOTHER_WE2_MSK	(MSK(6) << SEAD_PI_TIMOTHER_WE2_SHF)

/* bit 31:26 : */
#define SEAD_PI_TIMOTHER_ADH_SHF	26
#define SEAD_PI_TIMOTHER_ADH_MSK	(MSK(6) << SEAD_PI_TIMOTHER_ADH_SHF)



/************************************************************************
 ************************************************************************
 *  SEAD FPGA, GENERAL CONTROL REGISTERS:
 ************************************************************************
 ************************************************************************/

/************************************************************************
 *  NMI STATUS, ACK AND PSU STANDBY CONTROL :
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define SEAD_NMISTATUS              	(SEAD_PI_BASE + 0x0040)
#define SEAD_NMIACK                 	(SEAD_PI_BASE + 0x0048)

/*  Address SEAD_PI_BASE + 0x50 is used for different purposes on
 *  SEAD and SEAD-2 boards.
 *  On SEAD it is used for SW Power Off.
 *  On SEAD-2 it is used for SW reset.
 */
#define SEAD_PSUSTBY                	(SEAD_PI_BASE + 0x0050) 
#define SEAD2_SWRESET			(SEAD_PI_BASE + 0x0050) 

/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: NMISTATUS ********/

/* bit 0: */
#define SEAD_NMISTATUS_FLAG_SHF		0
#define SEAD_NMISTATUS_FLAG_MSK		(MSK(1) << SEAD_NMISTATUS_FLAG_SHF)
#define SEAD_NMISTATUS_FLAG_BIT  	SEAD_NMISTATUS_FLAG_MSK

/* bit 1: */
#define SEAD_NMISTATUS_WERR_SHF		1
#define SEAD_NMISTATUS_WERR_MSK		(MSK(1) << SEAD_NMISTATUS_WERR_SHF)
#define SEAD_NMISTATUS_WERR_BIT  	SEAD_NMISTATUS_WERR_MSK

/******** reg: NMIACK ********/

/* bit 0: */
#define SEAD_NMIACK_ACK_SHF		0
#define SEAD_NMIACK_ACK_MSK		(MSK(1) << SEAD_NMIACK_ACK_SHF)
#define SEAD_NMIACK_ACK_BIT  		SEAD_NMIACK_ACK_MSK


/******** reg: PSUSTBY (SEAD only)  ********/

/* bits 7:0: STBY */
#define SEAD_PSUSTBY_STBY_SHF	    	0
#define SEAD_PSUSTBY_STBY_MSK	    	(MSK(8) << SEAD_PSUSTBY_STBY_SHF)
#define SEAD_PSUSTBY_STBY_GOSTBY   	0x4D     /* magic value to go stby  */


/******** reg: SWRESET (SEAD-2 only) ********/

#define SEAD2_SWRESET_SWRST_SHF	        0
#define SEAD2_SWRESET_SWRST_MSK		(MSK(8) << SEAD2_SWRESET_SWRST_SHF)
#define SEAD2_SWRESET_SWRST_GORESET	0x4D


/************************************************************************
 ************************************************************************
 *  SEAD FPGA, SDRAM CONTROLLER REGISTERS:
 ************************************************************************
 ************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define SEAD_SD_REGSSET			(SEAD_SD_BASE + 0x0008)
#define SEAD_SD_MRSCODE			(SEAD_SD_BASE + 0x0010)
#define SEAD_SD_CONFIG			(SEAD_SD_BASE + 0x0018)
#define SEAD_SD_LATENCIES		(SEAD_SD_BASE + 0x0020)
#define SEAD_SD_TREFRESH		(SEAD_SD_BASE + 0x0028)
#define SEAD_SD_SPDCNF			(SEAD_SD_BASE + 0x0040)
#define SEAD_SD_SPDADR			(SEAD_SD_BASE + 0x0048)
#define SEAD_SD_SPDDAT			(SEAD_SD_BASE + 0x0050)

/************************************************************************
 *      Register field encodings
*************************************************************************/

/******** reg: SD_REGSSET ********/

#define SEAD_SD_REGSSET_SET_SHF		0
#define SEAD_SD_REGSSET_SET_MSK		(MSK(1) << SEAD_SD_REGSSET_SET_SHF)
#define SEAD_SD_REGSSET_SET_BIT	        SEAD_SD_REGSSET_SET_MSK


/******** reg: SD_MRSCODE ********/

#define SEAD_SD_MRSCODE_WBL_SHF		9
#define SEAD_SD_MRSCODE_WBL_MSK		(MSK(1) << SEAD_SD_MRSCODE_WBL_SHF)
#define SEAD_SD_MRSCODE_TM_SHF		7
#define SEAD_SD_MRSCODE_TM_MSK		(MSK(2) << SEAD_SD_MRSCODE_TM_SHF)
#define SEAD_SD_MRSCODE_CL_SHF		4
#define SEAD_SD_MRSCODE_CL_MSK		(MSK(3) << SEAD_SD_MRSCODE_CL_SHF)
#define SEAD_SD_MRSCODE_BT_SHF		3
#define SEAD_SD_MRSCODE_BT_MSK		(MSK(1) << SEAD_SD_MRSCODE_BT_SHF)
#define SEAD_SD_MRSCODE_BL_SHF		0
#define SEAD_SD_MRSCODE_BL_MSK		(MSK(3) << SEAD_SD_MRSCODE_BL_SHF)


/******** reg: SD_CONFIG ********/

#define SEAD_SD_CONFIG_CSN_SHF		12
#define SEAD_SD_CONFIG_CSN_MSK        	(MSK(4) << SEAD_SD_CONFIG_CSN_SHF)
#define SEAD_SD_CONFIG_BANKN_SHF	8
#define SEAD_SD_CONFIG_BANKN_MSK	(MSK(4) << SEAD_SD_CONFIG_BANKN_SHF)
#define SEAD_SD_CONFIG_ROWW_SHF		4
#define SEAD_SD_CONFIG_ROWW_MSK		(MSK(4) << SEAD_SD_CONFIG_ROWW_SHF)
#define SEAD_SD_CONFIG_COLW_SHF		0
#define SEAD_SD_CONFIG_COLW_MSK		(MSK(4) << SEAD_SD_CONFIG_COLW_SHF)


/******** reg: SD_LATENCIES ********/

#define SEAD_SD_LATENCIES_TRP_SHF	12
#define SEAD_SD_LATENCIES_TRP_MSK	(MSK(4) << SEAD_SD_LATENCIES_TRP_SHF)
#define SEAD_SD_LATENCIES_TRP_MIN	2
#define SEAD_SD_LATENCIES_TRP_MAX	4
#define SEAD_SD_LATENCIES_TRAS_SHF	8
#define SEAD_SD_LATENCIES_TRAS_MSK	(MSK(4) << SEAD_SD_LATENCIES_TRAS_SHF)
#define SEAD_SD_LATENCIES_TRCD_SHF	4
#define SEAD_SD_LATENCIES_TRCD_MSK	(MSK(4) << SEAD_SD_LATENCIES_TRCD_SHF)
#define SEAD_SD_LATENCIES_TRCD_MIN	2
#define SEAD_SD_LATENCIES_TRCD_MAX	3
#define SEAD_SD_LATENCIES_TDPL_SHF	0
#define SEAD_SD_LATENCIES_TDPL_MSK	(MSK(4) << SEAD_SD_LATENCIES_TDPL_SHF)