gt64120.h

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

#define GT_PCI0_BARE_INTIODIS_SHF	3
#define GT_PCI0_BARE_INTIODIS_MSK	(MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
#define GT_PCI0_BARE_INTIODIS_BIT	GT_PCI0_BARE_INTIODIS_MSK

#define GT_PCI0_BARE_INTMEMDIS_SHF	4
#define GT_PCI0_BARE_INTMEMDIS_MSK	(MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
#define GT_PCI0_BARE_INTMEMDIS_BIT	GT_PCI0_BARE_INTMEMDIS_MSK

#define GT_PCI0_BARE_CS3BOOTDIS_SHF	5
#define GT_PCI0_BARE_CS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
#define GT_PCI0_BARE_CS3BOOTDIS_BIT	GT_PCI0_BARE_CS3BOOTDIS_MSK

#define GT_PCI0_BARE_CS20DIS_SHF	6
#define GT_PCI0_BARE_CS20DIS_MSK	(MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
#define GT_PCI0_BARE_CS20DIS_BIT	GT_PCI0_BARE_CS20DIS_MSK

#define GT_PCI0_BARE_SCS32DIS_SHF	7
#define GT_PCI0_BARE_SCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
#define GT_PCI0_BARE_SCS32DIS_BIT	GT_PCI0_BARE_SCS32DIS_MSK

#define GT_PCI0_BARE_SCS10DIS_SHF	8
#define GT_PCI0_BARE_SCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
#define GT_PCI0_BARE_SCS10DIS_BIT	GT_PCI0_BARE_SCS10DIS_MSK



/* INTRCAUSE Register */

#define GT_INTRCAUSE_INTSUM_SHF		0
#define GT_INTRCAUSE_INTSUM_MSK		(MSK(1) << GT_INTRCAUSE_INTSUM_SHF)
#define GT_INTRCAUSE_INTSUM_BIT		GT_INTRCAUSE_INTSUM_MSK

#define GT_INTRCAUSE_MEMOUT_SHF		1
#define GT_INTRCAUSE_MEMOUT_MSK		(MSK(1) << GT_INTRCAUSE_MEMOUT_SHF)
#define GT_INTRCAUSE_MEMOUT_BIT		GT_INTRCAUSE_MEMOUT_MSK

#define GT_INTRCAUSE_DMAOUT_SHF		2
#define GT_INTRCAUSE_DMAOUT_MSK		(MSK(1) << GT_INTRCAUSE_DMAOUT_SHF)
#define GT_INTRCAUSE_DMAOUT_BIT		GT_INTRCAUSE_DMAOUT_MSK

#define GT_INTRCAUSE_CPUOUT_SHF		3
#define GT_INTRCAUSE_CPUOUT_MSK		(MSK(1) << GT_INTRCAUSE_CPUOUT_SHF)
#define GT_INTRCAUSE_CPUOUT_BIT		GT_INTRCAUSE_CPUOUT_MSK

#define GT_INTRCAUSE_DMA0COMP_SHF	4
#define GT_INTRCAUSE_DMA0COMP_MSK	(MSK(1) << GT_INTRCAUSE_DMA0COMP_SHF)
#define GT_INTRCAUSE_DMA0COMP_BIT	GT_INTRCAUSE_DMA0COMP_MSK

#define GT_INTRCAUSE_DMA1COMP_SHF	5
#define GT_INTRCAUSE_DMA1COMP_MSK	(MSK(1) << GT_INTRCAUSE_DMA1COMP_SHF)
#define GT_INTRCAUSE_DMA1COMP_BIT	GT_INTRCAUSE_DMA1COMP_MSK

#define GT_INTRCAUSE_DMA2COMP_SHF	6
#define GT_INTRCAUSE_DMA2COMP_MSK	(MSK(1) << GT_INTRCAUSE_DMA2COMP_SHF)
#define GT_INTRCAUSE_DMA2COMP_BIT	GT_INTRCAUSE_DMA2COMP_MSK

#define GT_INTRCAUSE_DMA3COMP_SHF	7
#define GT_INTRCAUSE_DMA3COMP_MSK	(MSK(1) << GT_INTRCAUSE_DMA3COMP_SHF)
#define GT_INTRCAUSE_DMA3COMP_BIT	GT_INTRCAUSE_DMA3COMP_MSK

#define GT_INTRCAUSE_T0EXP_SHF		8
#define GT_INTRCAUSE_T0EXP_MSK		(MSK(1) << GT_INTRCAUSE_T0EXP_SHF)
#define GT_INTRCAUSE_T0EXP_BIT		GT_INTRCAUSE_T0EXP_MSK

#define GT_INTRCAUSE_T1EXP_SHF		9
#define GT_INTRCAUSE_T1EXP_MSK		(MSK(1) << GT_INTRCAUSE_T1EXP_SHF)
#define GT_INTRCAUSE_T1EXP_BIT		GT_INTRCAUSE_T1EXP_MSK

#define GT_INTRCAUSE_T2EXP_SHF		10
#define GT_INTRCAUSE_T2EXP_MSK		(MSK(1) << GT_INTRCAUSE_T2EXP_SHF)
#define GT_INTRCAUSE_T2EXP_BIT		GT_INTRCAUSE_T2EXP_MSK

#define GT_INTRCAUSE_T3EXP_SHF		11
#define GT_INTRCAUSE_T3EXP_MSK		(MSK(1) << GT_INTRCAUSE_T3EXP_SHF)
#define GT_INTRCAUSE_T3EXP_BIT		GT_INTRCAUSE_T3EXP_MSK

#define GT_INTRCAUSE_MASRDERR0_SHF	12
#define GT_INTRCAUSE_MASRDERR0_MSK	(MSK(1) << GT_INTRCAUSE_MASRDERR0_SHF)
#define GT_INTRCAUSE_MASRDERR0_BIT	GT_INTRCAUSE_MASRDERR0_MSK

#define GT_INTRCAUSE_SLVWRERR0_SHF	13
#define GT_INTRCAUSE_SLVWRERR0_MSK	(MSK(1) << GT_INTRCAUSE_SLVWRERR0_SHF)
#define GT_INTRCAUSE_SLVWRERR0_BIT	GT_INTRCAUSE_SLVWRERR0_MSK

#define GT_INTRCAUSE_MASWRERR0_SHF	14
#define GT_INTRCAUSE_MASWRERR0_MSK	(MSK(1) << GT_INTRCAUSE_MASWRERR0_SHF)
#define GT_INTRCAUSE_MASWRERR0_BIT	GT_INTRCAUSE_MASWRERR0_MSK

#define GT_INTRCAUSE_SLVRDERR0_SHF	15
#define GT_INTRCAUSE_SLVRDERR0_MSK	(MSK(1) << GT_INTRCAUSE_SLVRDERR0_SHF)
#define GT_INTRCAUSE_SLVRDERR0_BIT	GT_INTRCAUSE_SLVRDERR0_MSK

#define GT_INTRCAUSE_ADDRERR0_SHF	16
#define GT_INTRCAUSE_ADDRERR0_MSK	(MSK(1) << GT_INTRCAUSE_ADDRERR0_SHF)
#define GT_INTRCAUSE_ADDRERR0_BIT	GT_INTRCAUSE_ADDRERR0_MSK

#define GT_INTRCAUSE_MEMERR_SHF		17
#define GT_INTRCAUSE_MEMERR_MSK		(MSK(1) << GT_INTRCAUSE_MEMERR_SHF)
#define GT_INTRCAUSE_MEMERR_BIT		GT_INTRCAUSE_MEMERR_MSK

#define GT_INTRCAUSE_MASABORT0_SHF	18
#define GT_INTRCAUSE_MASABORT0_MSK	(MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
#define GT_INTRCAUSE_MASABORT0_BIT	GT_INTRCAUSE_MASABORT0_MSK

#define GT_INTRCAUSE_TARABORT0_SHF	19
#define GT_INTRCAUSE_TARABORT0_MSK	(MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
#define GT_INTRCAUSE_TARABORT0_BIT	GT_INTRCAUSE_TARABORT0_MSK

#define GT_INTRCAUSE_RETRYCTR0_SHF	20
#define GT_INTRCAUSE_RETRYCTR0_MSK	(MSK(1) << GT_INTRCAUSE_RETRYCTR0_SHF)
#define GT_INTRCAUSE_RETRYCTR0_BIT	GT_INTRCAUSE_RETRYCTR0_MSK

#define GT_INTRCAUSE_CPUINT_SHF		21
#define GT_INTRCAUSE_CPUINT_MSK		(MSK(5) << GT_INTRCAUSE_CPUINT_SHF)

#define GT_INTRCAUSE_PCIINT_SHF		26
#define GT_INTRCAUSE_PCIINT_MSK		(MSK(4) << GT_INTRCAUSE_PCIINT_SHF)

#define GT_INTRCAUSE_CPUINTSUM_SHF	30
#define GT_INTRCAUSE_CPUINTSUM_MSK	(MSK(1) << GT_INTRCAUSE_CPUINTSUM_SHF)
#define GT_INTRCAUSE_CPUINTSUM_BIT	GT_INTRCAUSE_CPUINTSUM_MSK

#define GT_INTRCAUSE_PCIINTSUM_SHF	31
#define GT_INTRCAUSE_PCIINTSUM_MSK	(MSK(1) << GT_INTRCAUSE_PCIINTSUM_SHF)
#define GT_INTRCAUSE_PCIINTSUM_BIT	GT_INTRCAUSE_PCIINTSUM_MSK


/* CPUINT_MASK Register */

#define GT_CPUINT_MASK_MEMOUT_SHF	1
#define GT_CPUINT_MASK_MEMOUT_MSK	(MSK(1) << GT_CPUINT_MASK_MEMOUT_SHF)
#define GT_CPUINT_MASK_MEMOUT_BIT	GT_CPUINT_MASK_MEMOUT_MSK

#define GT_CPUINT_MASK_DMAOUT_SHF	2
#define GT_CPUINT_MASK_DMAOUT_MSK	(MSK(1) << GT_CPUINT_MASK_DMAOUT_SHF)
#define GT_CPUINT_MASK_DMAOUT_BIT	GT_CPUINT_MASK_DMAOUT_MSK

#define GT_CPUINT_MASK_CPUOUT_SHF	3
#define GT_CPUINT_MASK_CPUOUT_MSK	(MSK(1) << GT_CPUINT_MASK_CPUOUT_SHF)
#define GT_CPUINT_MASK_CPUOUT_BIT	GT_CPUINT_MASK_CPUOUT_MSK

#define GT_CPUINT_MASK_DMA0COMP_SHF	4
#define GT_CPUINT_MASK_DMA0COMP_MSK	(MSK(1) << GT_CPUINT_MASK_DMA0COMP_SHF)
#define GT_CPUINT_MASK_DMA0COMP_BIT	GT_CPUINT_MASK_DMA0COMP_MSK

#define GT_CPUINT_MASK_DMA1COMP_SHF	5
#define GT_CPUINT_MASK_DMA1COMP_MSK	(MSK(1) << GT_CPUINT_MASK_DMA1COMP_SHF)
#define GT_CPUINT_MASK_DMA1COMP_BIT	GT_CPUINT_MASK_DMA1COMP_MSK

#define GT_CPUINT_MASK_DMA2COMP_SHF	6
#define GT_CPUINT_MASK_DMA2COMP_MSK	(MSK(1) << GT_CPUINT_MASK_DMA2COMP_SHF)
#define GT_CPUINT_MASK_DMA2COMP_BIT	GT_CPUINT_MASK_DMA2COMP_MSK

#define GT_CPUINT_MASK_DMA3COMP_SHF	7
#define GT_CPUINT_MASK_DMA3COMP_MSK	(MSK(1) << GT_CPUINT_MASK_DMA3COMP_SHF)
#define GT_CPUINT_MASK_DMA3COMP_BIT	GT_CPUINT_MASK_DMA3COMP_MSK

#define GT_CPUINT_MASK_T0EXP_SHF	8
#define GT_CPUINT_MASK_T0EXP_MSK	(MSK(1) << GT_CPUINT_MASK_T0EXP_SHF)
#define GT_CPUINT_MASK_T0EXP_BIT	GT_CPUINT_MASK_T0EXP_MSK

#define GT_CPUINT_MASK_T1EXP_SHF	9
#define GT_CPUINT_MASK_T1EXP_MSK	(MSK(1) << GT_CPUINT_MASK_T1EXP_SHF)
#define GT_CPUINT_MASK_T1EXP_BIT	GT_CPUINT_MASK_T1EXP_MSK

#define GT_CPUINT_MASK_T2EXP_SHF	10
#define GT_CPUINT_MASK_T2EXP_MSK	(MSK(1) << GT_CPUINT_MASK_T2EXP_SHF)
#define GT_CPUINT_MASK_T2EXP_BIT	GT_CPUINT_MASK_T2EXP_MSK

#define GT_CPUINT_MASK_T3EXP_SHF	11
#define GT_CPUINT_MASK_T3EXP_MSK	(MSK(1) << GT_CPUINT_MASK_T3EXP_SHF)
#define GT_CPUINT_MASK_T3EXP_BIT	GT_CPUINT_MASK_T3EXP_MSK

#define GT_CPUINT_MASK_MASRDERR0_SHF	12
#define GT_CPUINT_MASK_MASRDERR0_MSK	(MSK(1) << GT_CPUINT_MASK_MASRDERR0_SHF)
#define GT_CPUINT_MASK_MASRDERR0_BIT	GT_CPUINT_MASK_MASRDERR0_MSK

#define GT_CPUINT_MASK_SLVWRERR0_SHF	13
#define GT_CPUINT_MASK_SLVWRERR0_MSK	(MSK(1) << GT_CPUINT_MASK_SLVWRERR0_SHF)
#define GT_CPUINT_MASK_SLVWRERR0_BIT	GT_CPUINT_MASK_SLVWRERR0_MSK

#define GT_CPUINT_MASK_MASWRERR0_SHF	14
#define GT_CPUINT_MASK_MASWRERR0_MSK	(MSK(1) << GT_CPUINT_MASK_MASWRERR0_SHF)
#define GT_CPUINT_MASK_MASWRERR0_BIT	GT_CPUINT_MASK_MASWRERR0_MSK

#define GT_CPUINT_MASK_SLVRDERR0_SHF	15
#define GT_CPUINT_MASK_SLVRDERR0_MSK	(MSK(1) << GT_CPUINT_MASK_SLVRDERR0_SHF)
#define GT_CPUINT_MASK_SLVRDERR0_BIT	GT_CPUINT_MASK_SLVRDERR0_MSK

#define GT_CPUINT_MASK_ADDRERR0_SHF	16
#define GT_CPUINT_MASK_ADDRERR0_MSK	(MSK(1) << GT_CPUINT_MASK_ADDRERR0_SHF)
#define GT_CPUINT_MASK_ADDRERR0_BIT	GT_CPUINT_MASK_ADDRERR0_MSK

#define GT_CPUINT_MASK_MEMERR_SHF	17
#define GT_CPUINT_MASK_MEMERR_MSK	(MSK(1) << GT_CPUINT_MASK_MEMERR_SHF)
#define GT_CPUINT_MASK_MEMERR_BIT	GT_CPUINT_MASK_MEMERR_MSK

#define GT_CPUINT_MASK_MASABORT0_SHF	18
#define GT_CPUINT_MASK_MASABORT0_MSK	(MSK(1) << GT_CPUINT_MASK_MASABORT0_SHF)
#define GT_CPUINT_MASK_MASABORT0_BIT	GT_CPUINT_MASK_MASABORT0_MSK

#define GT_CPUINT_MASK_TARABORT0_SHF	19
#define GT_CPUINT_MASK_TARABORT0_MSK	(MSK(1) << GT_CPUINT_MASK_TARABORT0_SHF)
#define GT_CPUINT_MASK_TARABORT0_BIT	GT_CPUINT_MASK_TARABORT0_MSK

#define GT_CPUINT_MASK_RETRYCTR0_SHF	20
#define GT_CPUINT_MASK_RETRYCTR0_MSK	(MSK(1) << GT_CPUINT_MASK_RETRYCTR0_SHF)
#define GT_CPUINT_MASK_RETRYCTR0_BIT	GT_CPUINT_MASK_RETRYCTR0_MSK

#define GT_CPUINT_MASK_PCIINT_SHF	26
#define GT_CPUINT_MASK_PCIINT_MSK	(MSK(4) << GT_CPUINT_MASK_PCIINT_SHF)



#define GT_PCI0_CFGADDR_REGNUM_SHF	2
#define GT_PCI0_CFGADDR_REGNUM_MSK	(MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
#define GT_PCI0_CFGADDR_FUNCTNUM_SHF	8
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK    (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
#define GT_PCI0_CFGADDR_DEVNUM_SHF	11
#define GT_PCI0_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
#define GT_PCI0_CFGADDR_BUSNUM_SHF	16
#define GT_PCI0_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_SHF	31
#define GT_PCI0_CFGADDR_CONFIGEN_MSK	(MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_BIT	GT_PCI0_CFGADDR_CONFIGEN_MSK


#define GT_TCCTRL_ENTC0_SHF		0
#define GT_TCCTRL_ENTC0_MSK		(MSK(1) << GT_TCCTRL_ENTC0_SHF)
#define GT_TCCTRL_ENTC0_BIT		GT_TCCTRL_ENTC0_MSK
#define GT_TCCTRL_SETC0_SHF		1
#define GT_TCCTRL_SETC0_MSK		(MSK(1) << GT_TCCTRL_SETC0_SHF)
#define GT_TCCTRL_SETC0_TIMER		GT_TCCTRL_SETC0_MSK

#define GT_TCCTRL_ENTC1_SHF		2
#define GT_TCCTRL_ENTC1_MSK		(MSK(1) << GT_TCCTRL_ENTC1_SHF)
#define GT_TCCTRL_ENTC1_BIT		GT_TCCTRL_ENTC1_MSK
#define GT_TCCTRL_SETC1_SHF		3
#define GT_TCCTRL_SETC1_MSK		(MSK(1) << GT_TCCTRL_SETC1_SHF)
#define GT_TCCTRL_SETC1_TIMER		GT_TCCTRL_SETC1_MSK

#define GT_TCCTRL_ENTC2_SHF		4
#define GT_TCCTRL_ENTC2_MSK		(MSK(1) << GT_TCCTRL_ENTC2_SHF)
#define GT_TCCTRL_ENTC2_BIT		GT_TCCTRL_ENTC2_MSK
#define GT_TCCTRL_SETC2_SHF		5
#define GT_TCCTRL_SETC2_MSK		(MSK(1) << GT_TCCTRL_SETC2_SHF)
#define GT_TCCTRL_SETC2_TIMER		GT_TCCTRL_SETC2_MSK

#define GT_TCCTRL_ENTC3_SHF		6
#define GT_TCCTRL_ENTC3_MSK		(MSK(1) << GT_TCCTRL_ENTC3_SHF)
#define GT_TCCTRL_ENTC3_BIT		GT_TCCTRL_ENTC3_MSK
#define GT_TCCTRL_SETC3_SHF		7
#define GT_TCCTRL_SETC3_MSK		(MSK(1) << GT_TCCTRL_SETC3_SHF)
#define GT_TCCTRL_SETC3_TIMER		GT_TCCTRL_SETC4_MSK


/* PCI BARs */
#define GT_BAR_SCS10_POS		PCI_BAR(0)
#define GT_BAR_SCS32_POS		PCI_BAR(1)
#define GT_BAR_INTERNAL_MEM_POS		PCI_BAR(4)

/************************************************************************
 *  Misc
 ************************************************************************/


#define GT_DEF_BASE		0x14000000	/* Base address after reset   */
#define GT_DEV		        0		/* Galileo PCI device number  */
#define GT_DEF_PCI0_MEM0_BASE	0x12000000	/* PCI0 Mem0 base after reset */
#define GT_MAX_BANKSIZE		(256 * 1024 * 1024)   /* Max 256MB bank	      */
#define GT_LATTIM_MIN    	6		      /* Minimum lat	      */


#ifdef _ASSEMBLER_

#ifdef EB

#define GT_SW( data, ofs, base ) \
		.##set noat; \
		SWAPEND32( data, AT, v1 ); \
		.##set at; \
		sw	data, ofs(base)

#define GT_LW( data, ofs, base ) \
		lw	data,   ofs(base); \
		.##set noat; \
		SWAPEND32( data, AT, v1 ); \
		.##set at

#else  /* #ifdef EB */

#define GT_SW( data, ofs, base )\
		sw	data, ofs(base)

#define GT_LW( data, ofs, base )\
		lw	data, ofs(base)

#endif	/* #ifdef EB */


#else   /* #ifdef _ASSEMBLER_ */

#define GT_W32(base, ofs, data)	  REGW32LE( (&((volatile UINT8*)(base))[ofs]), data)
#define GT_L32(base, ofs, data)	  REGR32LE( (&((volatile UINT8*)(base))[ofs]), data)

/* Function in flash for writing GT64120 register */
UINT32 gt64120_write_reg( UINT32 addr, UINT32 data );

#endif  /* #ifdef _ASSEMBLER_ */



#endif /* #ifndef GT64120_H */