msc01_pci.h

来自「MIPS YAMON, a famous monitor inc. source」· C头文件 代码 · 共 411 行 · 第 1/2 页

/* ##########################################################################
 *
 *  PCI bridge header file
 *
 * ##########################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
 * this code does not give recipient any license to any intellectual
 * property rights, including any patent rights, that cover this code.
 *
 * This code shall not be exported, reexported, transferred, or released,
 * directly or indirectly, in violation of the law of any country or
 * international law, regulation, treaty, Executive Order, statute,
 * amendments or supplements thereto. Should a conflict arise regarding the
 * export, reexport, transfer, or release of this code, the laws of the
 * United States of America shall be the governing law.
 *
 * This code constitutes one or more of the following: commercial computer
 * software, commercial computer software documentation or other commercial
 * items. If the user of this code, or any related documentation of any
 * kind, including related technical data or manuals, is an agency,
 * department, or other entity of the United States government
 * ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this code, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
 * of this code by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms
 * and conditions covering this code from MIPS Technologies or an authorized
 * third party.
 *
 *
 *
 * 
 * mips_end_of_legal_notice
 * 
 *
 * ###########################################################################
 */

#ifndef MSC01_PCI_H
#define MSC01_PCI_H

/*****************************************************************************
 * Register offset addresses
 ****************************************************************************/

/* PCI bridge ID in MSC01_PCI_ID */
#define MSC01_ID_PCI                    0x82

#define MSC01_PCI_ID_OFS		0x0000
#define MSC01_PCI_SC2PMBASL_OFS		0x0208
#define MSC01_PCI_SC2PMMSKL_OFS		0x0218
#define MSC01_PCI_SC2PMMAPL_OFS		0x0228
#define MSC01_PCI_SC2PIOBASL_OFS	0x0248
#define MSC01_PCI_SC2PIOMSKL_OFS	0x0258
#define MSC01_PCI_SC2PIOMAPL_OFS	0x0268
#define MSC01_PCI_P2SCMSKL_OFS		0x0308
#define MSC01_PCI_P2SCMAPL_OFS		0x0318
#define MSC01_PCI_INTCFG_OFS		0x0600
#define MSC01_PCI_INTSTAT_OFS		0x0608
#define MSC01_PCI_CFGADDR_OFS		0x0610
#define MSC01_PCI_CFGDATA_OFS		0x0618
#define MSC01_PCI_IACK_OFS		0x0620
#define MSC01_PCI_HEAD0_OFS		0x2000  /* DevID, VendorID */
#define MSC01_PCI_HEAD1_OFS		0x2008  /* Status, Command */
#define MSC01_PCI_HEAD2_OFS		0x2010  /* Class code, RevID */
#define MSC01_PCI_HEAD3_OFS		0x2018  /* bist, header, latency */
#define MSC01_PCI_HEAD4_OFS		0x2020  /* BAR 0 */
#define MSC01_PCI_HEAD5_OFS		0x2028  /* BAR 1 */
#define MSC01_PCI_HEAD6_OFS		0x2030  /* BAR 2 */
#define MSC01_PCI_HEAD7_OFS		0x2038  /* BAR 3 */
#define MSC01_PCI_HEAD8_OFS		0x2040  /* BAR 4 */
#define MSC01_PCI_HEAD9_OFS		0x2048  /* BAR 5 */
#define MSC01_PCI_HEAD10_OFS		0x2050  /* CardBus CIS Ptr */
#define MSC01_PCI_HEAD11_OFS		0x2058  /* SubSystem ID, -VendorID */
#define MSC01_PCI_HEAD12_OFS		0x2060  /* ROM BAR */
#define MSC01_PCI_HEAD13_OFS		0x2068  /* Capabilities ptr */
#define MSC01_PCI_HEAD14_OFS		0x2070  /* reserved */
#define MSC01_PCI_HEAD15_OFS		0x2078  /* Maxl, ming, intpin, int */
#define MSC01_PCI_BAR0_OFS		0x2220
#define MSC01_PCI_CFG_OFS		0x2380
#define MSC01_PCI_SWAP_OFS		0x2388


/*****************************************************************************
 * Register encodings
 ****************************************************************************/

#define MSC01_PCI_ID_ID_SHF		16
#define MSC01_PCI_ID_ID_MSK		0x00ff0000
#define MSC01_PCI_ID_MAR_SHF		8
#define MSC01_PCI_ID_MAR_MSK		0x0000ff00
#define MSC01_PCI_ID_MIR_SHF		0
#define MSC01_PCI_ID_MIR_MSK		0x000000ff

#define MSC01_PCI_SC2PMBASL_BAS_SHF	24
#define MSC01_PCI_SC2PMBASL_BAS_MSK	0xff000000

#define MSC01_PCI_SC2PMMSKL_MSK_SHF	24
#define MSC01_PCI_SC2PMMSKL_MSK_MSK	0xff000000

#define MSC01_PCI_SC2PMMAPL_MAP_SHF	24
#define MSC01_PCI_SC2PMMAPL_MAP_MSK	0xff000000

#define MSC01_PCI_SC2PIOBASL_BAS_SHF	24
#define MSC01_PCI_SC2PIOBASL_BAS_MSK	0xff000000

#define MSC01_PCI_SC2PIOMSKL_MSK_SHF	24
#define MSC01_PCI_SC2PIOMSKL_MSK_MSK	0xff000000

#define MSC01_PCI_SC2PIOMAPL_MAP_SHF	24
#define MSC01_PCI_SC2PIOMAPL_MAP_MSK	0xff000000

#define MSC01_PCI_P2SCMSKL_MSK_SHF	20
#define MSC01_PCI_P2SCMSKL_MSK_MSK	0xfff00000

#define MSC01_PCI_P2SCMAPL_MAP_SHF	20
#define MSC01_PCI_P2SCMAPL_MAP_MSK	0xfff00000

#define MSC01_PCI_INTCFG_RST_SHF        10
#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
#define MSC01_PCI_INTCFG_MWE_SHF        9
#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
#define MSC01_PCI_INTCFG_DTO_SHF        8
#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
#define MSC01_PCI_INTCFG_MA_SHF         7
#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
#define MSC01_PCI_INTCFG_TA_SHF         6
#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
#define MSC01_PCI_INTCFG_RTY_SHF        5
#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
#define MSC01_PCI_INTCFG_MWP_SHF        4
#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
#define MSC01_PCI_INTCFG_MRP_SHF        3
#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
#define MSC01_PCI_INTCFG_SWP_SHF        2
#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
#define MSC01_PCI_INTCFG_SRP_SHF        1
#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
#define MSC01_PCI_INTCFG_SE_SHF         0
#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
#define MSC01_PCI_INTCFG_SE_BIT         0x00000001

#define MSC01_PCI_INTSTAT_RST_SHF       10
#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
#define MSC01_PCI_INTSTAT_MWE_SHF       9
#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
#define MSC01_PCI_INTSTAT_DTO_SHF       8
#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
#define MSC01_PCI_INTSTAT_MA_SHF        7
#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
#define MSC01_PCI_INTSTAT_TA_SHF        6
#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
#define MSC01_PCI_INTSTAT_RTY_SHF       5
#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
#define MSC01_PCI_INTSTAT_MWP_SHF       4
#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
#define MSC01_PCI_INTSTAT_MRP_SHF       3
#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
#define MSC01_PCI_INTSTAT_SWP_SHF       2
#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
#define MSC01_PCI_INTSTAT_SRP_SHF       1
#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002