mips.h

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

999:

#define ICACHE_INDEX_INVALIDATE_OP(index,scratch)		  \
	    ICACHE_INVALIDATE_WORKAROUND(scratch);		  \
	    cache ICACHE_INDEX_INVALIDATE, 0(index)

#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch)			  \
	    ICACHE_INVALIDATE_WORKAROUND(scratch);		  \
	    cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr)

#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg)			  \
	    cache   SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg);

#define SCACHE_INDEX_WRITEBACK_INVALIDATE_OP(reg)			  \
	    cache   SCACHE_INDEX_WRITEBACK_INVALIDATE, 0(reg);

/* Config1 cache field decoding */
#define CACHE_CALC_SPW(s)	( 64 << (s) )
#define CACHE_CALC_LS(l)	( (l) ? 2 << (l) : 0 )
#define CACHE_CALC_BPW(l,s)	( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) )
#define CACHE_CALC_ASSOC(a)	( (a) + 1 )


/**** Move from/to Coprocessor operations ****/

/*  We use ssnop instead of nop operations in order to handle 
 *  superscalar CPUs.
 *  The "sll zero,zero,1" notation is compiler backwards compatible.
 */
#define SSNOP   sll zero,zero,1
#define NOPS	SSNOP; SSNOP; SSNOP; SSNOP

/*  Workaround for bug in early revisions of MIPS 4K family of 
 *  processors.
 *
 *  This concerns the nop instruction before mtc0 in the 
 *  MTC0 macro below.
 *
 *  The bug is described in :
 *
 *  MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
 *  MIPS Document No: MD00003
 *
 *  The bug is identified as : C27
 */

#define MTC0(src, dst)       \
		nop;	     \
	        mtc0 src,dst;\
		NOPS

#define DMTC0(src, dst)       \
		nop;	      \
	        dmtc0 src,dst;\
		NOPS

#define MFC0(dst, src)       \
	  	mfc0 dst,src

#define DMFC0(dst, src)       \
	  	dmfc0 dst,src

#define MFC0_SEL_OPCODE(dst, src, sel)\
	  	.##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel))

#define MTC0_SEL_OPCODE(src, dst, sel)\
	  	.##word (0x40800000 | ((src)<<16) | ((dst)<<11) | (sel));\
		NOPS

#define LDC1(dst, src, offs)\
		.##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs))

#define SDC1(src, dst, offs)\
		.##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs))

/* Release 2 */
#define RDPGPR( rd, rt )\
		.##word (0x41400000 | ((rd) <<11) | (rt<<16))

#define WRPGPR( rd, rt )\
		.##word (0x41c00000 | ((rd) <<11) | (rt<<16))


/* Instruction opcode fields */
#define OPC_SPECIAL   0x0
#define OPC_REGIM     0x1
#define OPC_J         0x2
#define OPC_JAL	      0x3
#define OPC_BEQ	      0x4
#define OPC_BNE	      0x5
#define OPC_BLEZ      0x6
#define OPC_BGTZ      0x7
#define OPC_COP1      0x11
#define OPC_JALX      0x1D
#define OPC_BEQL      0x14
#define OPC_BNEL      0x15
#define OPC_BLEZL     0x16
#define OPC_BGTZL     0x17

/* Instruction function fields */
#define FUNC_JR	      0x8
#define FUNC_JALR     0x9

/* Instruction rt fields */
#define RT_BLTZ	      0x0
#define RT_BGEZ	      0x1
#define RT_BLTZL      0x2
#define RT_BGEZL      0x3
#define RT_BLTZAL     0x10
#define RT_BGEZAL     0x11
#define RT_BLTZALL    0x12
#define RT_BGEZALL    0x13

/* Instruction rs fields */
#define RS_BC1	      0x08

/* Access macros for instruction fields */
#define MIPS_OPCODE( instr)	((instr) >> 26)
#define MIPS_FUNCTION(instr)	((instr) & MSK(6))
#define MIPS_RT(instr)		(((instr) >> 16) & MSK(5))
#define MIPS_RS(instr)		(((instr) >> 21) & MSK(5))
#define MIPS_OFFSET(instr)	((instr) & 0xFFFF)
#define MIPS_TARGET(instr)	((instr) & MSK(26))

/* Instructions */
#define OPCODE_DERET		0x4200001f
#define OPCODE_BREAK	  	0x0005000d
#define OPCODE_NOP		0
#define OPCODE_JUMP(addr)	( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) )

#define DERET			.##word OPCODE_DERET

/* MIPS16e opcodes and instruction field access macros */

#define MIPS16E_OPCODE(inst)		(((inst) >> 11) & 0x1f)
#define MIPS16E_I8_FUNCTION(inst)	(((inst) >>  8) & 0x7)
#define MIPS16E_X(inst) 		(((inst) >> 26) & 0x1)
#define MIPS16E_RR_FUNCTION(inst)	(((inst) >>  0) & 0x1f)
#define MIPS16E_RY(inst)		(((inst) >>  5) & 0x3)
#define MIPS16E_OPC_EXTEND		0x1e
#define MIPS16E_OPC_JAL_X		0x03
#define MIPS16E_OPC_B			0x02
#define MIPS16E_OPC_BEQZ		0x04
#define MIPS16E_OPC_BNEZ		0x05
#define MIPS16E_OPC_I8			0x0c
#define MIPS16E_I8_FUNC_BTEQZ		0x00
#define MIPS16E_I8_FUNC_BTNEZ		0x01
#define MIPS16E_X_JALX			0x01
#define MIPS16E_OPC_RR			0x1d
#define MIPS16E_RR_FUNC_JALRC		0x00
#define MIPS16E_RR_RY_JRRX		0x00
#define MIPS16E_RR_RY_JRRA		0x01
#define MIPS16E_RR_RY_JALR		0x02
#define MIPS16E_RR_RY_JRCRX		0x04
#define MIPS16E_RR_RY_JRCRA		0x05
#define MIPS16E_RR_RY_JALRC		0x06

#define MIPS16E_OPCODE_BREAK		0xE805
#define MIPS16E_OPCODE_NOP		0x6500

/* MIPS reset vector */
#define MIPS_RESET_VECTOR       0x1fc00000

/* Clock periods per count register increment */
#define MIPS4K_COUNT_CLK_PER_CYCLE	2
#define MIPS5K_COUNT_CLK_PER_CYCLE	2
#define MIPS20Kc_COUNT_CLK_PER_CYCLE	1
#define MIPS24K_COUNT_CLK_PER_CYCLE     2
#define MIPSM4K_COUNT_CLK_PER_CYCLE     2

/**** MIPS 4K/5K families specific fields of CONFIG register ****/

#define C0_CONFIG_MIPS4K5K_K23_MSK   (MSK(3) << S_ConfigK23)
#define C0_CONFIG_MIPS4K5K_KU_MSK    (MSK(3) << S_ConfigKU)

/**** MIPS 20Kc specific fields of CONFIG register ****/

#define C0_CONFIG_MIPS20KC_EC_SHF    28
#define C0_CONFIG_MIPS20KC_EC_MSK    (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF)

#define C0_CONFIG_MIPS20KC_DD_SHF    27
#define C0_CONFIG_MIPS20KC_DD_MSK    (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF)
#define C0_CONFIG_MIPS20KC_DD_BIT    C0_CONFIG_MIPS20KC_DD_MSK

#define C0_CONFIG_MIPS20KC_LP_SHF    26
#define C0_CONFIG_MIPS20KC_LP_MSK    (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF)
#define C0_CONFIG_MIPS20KC_LP_BIT    C0_CONFIG_MIPS20KC_LP_MSK

#define C0_CONFIG_MIPS20KC_SP_SHF    25
#define C0_CONFIG_MIPS20KC_SP_MSK    (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF)
#define C0_CONFIG_MIPS20KC_SP_BIT    C0_CONFIG_MIPS20KC_SP_MSK

#define C0_CONFIG_MIPS20KC_TI_SHF    24
#define C0_CONFIG_MIPS20KC_TI_MSK    (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF)
#define C0_CONFIG_MIPS20KC_TI_BIT    C0_CONFIG_MIPS20KC_TI_MSK


/* TBD : Until these appear in ArchDefs.h */
#define R_C0_DTagLo	        28
#define R_C0_SelDTagLo	        2
#define R_C0_DTagHi	        29
#define R_C0_SelDTagHi	        2

#define R_C0_TraceControl       23
#define R_C0_SelTraceControl	1
#define R_C0_TraceControl2	23
#define R_C0_SelTraceControl2	2
#define R_C0_UserTraceData	23
#define R_C0_SelUserTraceData	3
#define R_C0_TraceBPC		23
#define R_C0_SelTraceBPC	4

#define R_C0_DErrCtl		26
#define R_C0_SelDErrCtl		0
#define R_C0_IErrCtl		26
#define R_C0_SelIErrCtl		1

#define R_C0_ITagLo		28
#define R_C0_SelITagLo		0
#define R_C0_DTagLo		28
#define R_C0_SelDTagLo		2
#define R_C0_L23TagLo	        28
#define R_C0_SelL23TagLo	4

#define R_C0_IDataLo		28
#define R_C0_SelIDataLo		1
#define R_C0_DDataLo		28
#define R_C0_SelDDataLo		3
#define R_C0_L23DataLo		28
#define R_C0_SelL23DataLo	5

#define R_C0_ITagHi		29
#define R_C0_SelITagHi		0
#define R_C0_DTagHi		29
#define R_C0_SelDTagHi		2
#define R_C0_L23TagHi		29
#define R_C0_SelL23TagHi	4

#define R_C0_IDataHi		29
#define R_C0_SelIDataHi		1
#define R_C0_DDataHi		29
#define R_C0_SelDDataHi		3
#define R_C0_L23DataHi		29
#define R_C0_SelL23DataHi	5

#define R_C0_IWatchLo0		18
#define R_C0_SelIWatchLo0	0
#define R_C0_IWatchHi0		19
#define R_C0_SelIWatchHi0       0
#define R_C0_IWatchLo1		18
#define R_C0_SelIWatchLo1       1
#define R_C0_IWatchHi1		19
#define R_C0_SelIWatchHi1       1
#define R_C0_DWatchLo0		18
#define R_C0_SelDWatchLo0       2
#define R_C0_DWatchHi0		19
#define R_C0_SelDWatchHi0       2
#define R_C0_DWatchLo1		18
#define R_C0_SelDWatchLo1       3
#define R_C0_DWatchHi1		19
#define R_C0_SelDWatchHi1       3

#define S_ConfigMM              18     /* 24K specific, merging enable/disable */
#define M_ConfigMM              (0x1 << S_ConfigMM)

#endif /* #ifndef MIPS_H */