mips.h

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/************************************************************************
 *
 *  mips.h
 *
 *  MIPS processor definitions
 *
 *  The basic CPU definitions are found in the file ArchDefs.h, which
 *  is included by mips.h.
 *
 *  mips.h implements aliases for some of the definitions in ArchDefs.h
 *  and adds various definitions.
 *
 * ######################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
 * this code does not give recipient any license to any intellectual
 * property rights, including any patent rights, that cover this code.
 *
 * This code shall not be exported, reexported, transferred, or released,
 * directly or indirectly, in violation of the law of any country or
 * international law, regulation, treaty, Executive Order, statute,
 * amendments or supplements thereto. Should a conflict arise regarding the
 * export, reexport, transfer, or release of this code, the laws of the
 * United States of America shall be the governing law.
 *
 * This code constitutes one or more of the following: commercial computer
 * software, commercial computer software documentation or other commercial
 * items. If the user of this code, or any related documentation of any
 * kind, including related technical data or manuals, is an agency,
 * department, or other entity of the United States government
 * ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this code, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
 * of this code by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms
 * and conditions covering this code from MIPS Technologies or an authorized
 * third party.
 *
 *
 *
 * 
 * mips_end_of_legal_notice
 * 
 *
 ************************************************************************/

#ifndef MIPS_H
#define MIPS_H

/************************************************************************
 *  Include files
 ************************************************************************/

#ifndef MIPS_Release2
#define MIPS_Release2
#endif
#include <ArchDefs.h>

/************************************************************************
 *  Definitions
*************************************************************************/

#ifndef MSK
#define MSK(n)			  ((1 << (n)) - 1)
#endif

/* CPU registers */
#define SYS_CPUREG_ZERO	0
#define SYS_CPUREG_AT	1
#define SYS_CPUREG_V0	2
#define SYS_CPUREG_V1	3
#define SYS_CPUREG_A0	4
#define SYS_CPUREG_A1	5
#define SYS_CPUREG_A2	6
#define SYS_CPUREG_A3	7
#define SYS_CPUREG_T0	8
#define SYS_CPUREG_T1	9
#define SYS_CPUREG_T2	10
#define SYS_CPUREG_T3	11
#define SYS_CPUREG_T4	12
#define SYS_CPUREG_T5	13
#define SYS_CPUREG_T6	14
#define SYS_CPUREG_T7	15
#define SYS_CPUREG_S0	16
#define SYS_CPUREG_S1	17
#define SYS_CPUREG_S2	18
#define SYS_CPUREG_S3	19
#define SYS_CPUREG_S4	20
#define SYS_CPUREG_S5	21
#define SYS_CPUREG_S6	22
#define SYS_CPUREG_S7	23
#define SYS_CPUREG_T8	24
#define SYS_CPUREG_T9	25
#define SYS_CPUREG_K0	26
#define SYS_CPUREG_K1	27
#define SYS_CPUREG_GP	28
#define SYS_CPUREG_SP	29
#define SYS_CPUREG_S8	30
#define SYS_CPUREG_FP	SYS_CPUREG_S8		
#define SYS_CPUREG_RA	31


/* CPU register fp ($30) has an alias s8 */
#define s8		fp


/* C0_CONFIG register encoding */

/*  WC field.
 *
 *  This feature is present specifically to support configuration
 *  testing of the core in a lead vehicle, and is not supported
 *  in any other environment.  Attempting to use this feature
 *  outside of the scope of a lead vehicle is a violation of the
 *  MIPS Architecture, and may cause unpredictable operation of
 *  the processor.
 */
#define C0_CONFIG_WC_SHF		19
#define C0_CONFIG_WC_MSK    		(MSK(1) << C0_CONFIG_WC_SHF)
#define C0_CONFIG_WC_BIT		C0_CONFIG_WC_MSK


/* C0_Status register encoding */

/*  Note that the the definitions below indicate the interrupt number
 *  rather than the mask.
 *  (0..1 for SW interrupts and 2...7 for HW interrupts)
 */
#define C0_STATUS_IM_SW0		(S_StatusIM0 - S_StatusIM)
#define C0_STATUS_IM_SW1		(S_StatusIM1 - S_StatusIM)
#define C0_STATUS_IM_HW0		(S_StatusIM2 - S_StatusIM)
#define C0_STATUS_IM_HW1		(S_StatusIM3 - S_StatusIM)
#define C0_STATUS_IM_HW2		(S_StatusIM4 - S_StatusIM)
#define C0_STATUS_IM_HW3		(S_StatusIM5 - S_StatusIM)
#define C0_STATUS_IM_HW4		(S_StatusIM6 - S_StatusIM)
#define C0_STATUS_IM_HW5		(S_StatusIM7 - S_StatusIM)

/* Max interrupt code */
#define C0_STATUS_IM_MAX		C0_STATUS_IM_HW5


/* C0_PRId register encoding */

#define C0_PRID_COMP_NOT_MIPS32_64	0
#define C0_PRID_PRID_RM70XX  		0x27

#define MIPS_4Kc			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_Jade  << S_PRIdImp) )

#define MIPS_4Kmp			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_JadeLite  << S_PRIdImp) )

#define MIPS_4KEc			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_4KEc  << S_PRIdImp) )

#define MIPS_4KEc_R2			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_4KEc_R2 << S_PRIdImp) )

#define MIPS_4KEmp			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_4KEmp  << S_PRIdImp) )

#define MIPS_4KEmp_R2			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_4KEmp_R2 << S_PRIdImp) )

#define MIPS_4KSc			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_4KSc  << S_PRIdImp) )

#define MIPS_4KSd			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_4KSd  << S_PRIdImp) )

#define MIPS_5K				( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_Opal  << S_PRIdImp) )

#define MIPS_20Kc			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_Ruby  << S_PRIdImp) )

#define MIPS_M4K			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_M4K  <<  S_PRIdImp) )

#define MIPS_25Kf			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_Amethyst  << S_PRIdImp) )

#define MIPS_5KE			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_5KE   << S_PRIdImp) )

#define MIPS_24K			( (K_PRIdCoID_MIPS << S_PRIdCoID) | \
					  (K_PRIdImp_24K   << S_PRIdImp) )

#define QED_RM52XX			( (C0_PRID_COMP_NOT_MIPS32_64 << \
					      S_PRIdCoID) |	 \
					  (K_PRIdImp_R5200  << S_PRIdImp) )

#define QED_RM70XX			( (C0_PRID_COMP_NOT_MIPS32_64 << \
					      S_PRIdCoID) |	 \
					  (C0_PRID_PRID_RM70XX  << S_PRIdImp) )


/* cache operations */

#define CACHE_OP( code, type )			( ((code) << 2) | (type) )

#define ICACHE_INDEX_INVALIDATE			CACHE_OP(0x0, 0)
#define ICACHE_INDEX_LOAD_TAG			CACHE_OP(0x1, 0)
#define ICACHE_INDEX_STORE_TAG			CACHE_OP(0x2, 0)
#define DCACHE_INDEX_WRITEBACK_INVALIDATE	CACHE_OP(0x0, 1)
#define DCACHE_INDEX_LOAD_TAG			CACHE_OP(0x1, 1)
#define DCACHE_INDEX_STORE_TAG			CACHE_OP(0x2, 1)
#define SCACHE_INDEX_WRITEBACK_INVALIDATE	CACHE_OP(0x0, 3)
#define SCACHE_INDEX_STORE_TAG			CACHE_OP(0x2, 3)

#define ICACHE_ADDR_HIT_INVALIDATE		CACHE_OP(0x4, 0)
#define ICACHE_ADDR_FILL			CACHE_OP(0x5, 0)
#define ICACHE_ADDR_FETCH_LOCK			CACHE_OP(0x7, 0)
#define DCACHE_ADDR_HIT_INVALIDATE		CACHE_OP(0x4, 1)
#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE	CACHE_OP(0x5, 1)
#define DCACHE_ADDR_HIT_WRITEBACK		CACHE_OP(0x6, 1)
#define DCACHE_ADDR_FETCH_LOCK			CACHE_OP(0x7, 1)

#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE	CACHE_OP(0x5, 3)

/*  Workaround for bug in early revisions of MIPS 4K family of 
 *  processors. Only relevant in early engineering samples of test
 *  chips (RTL revision <= 3.0).
 *
 *  The bug is described in :
 *
 *  MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
 *  MIPS Document No: MD00003
 *
 *  The bug is identified as : C16
 */
#ifndef SET_MIPS0
#define SET_MIPS0()
#define SET_PUSH()
#define SET_POP()
#endif
#define ICACHE_INVALIDATE_WORKAROUND(reg) \
SET_PUSH();				  \
SET_MIPS0();				  \
	la     reg, 999f;		  \
SET_POP();				  \
	cache  ICACHE_ADDR_FILL, 0(reg);  \
	sync;				  \
	nop; nop; nop; nop;		  \