sys_cpu_s.s

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/************************************************************************
 *
 *  sys_cpu_s.S
 *
 *  cpu functions
 *
 * ######################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
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 * This code shall not be exported, reexported, transferred, or released,
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 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
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 * mips_end_of_legal_notice
 * 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <sys_api.h>
#include <mips.h>
#include <qed.h>
	
/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

	.set noreorder
			
/************************************************************************
 *
 *                          sys_cpu_icache_config
 *  Description :
 *  -------------
 *
 *  Configure icache
 *
 *  a0 holds the requested sets per way field
 *  a1 holds the requested line size (0 or hardware default) field
 *  a2 holds the requested associativity field
 *  a3 holds the reset value of CONFIG1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cpu_icache_config )

	/* Reserve space on stack */
	addiu	sp, -8*4

	/* Store return address, s0..s4 */
	sw	ra, 0(sp)
	sw	s0, 4(sp)
	sw	s1, 8(sp)
	sw	s2, 12(sp)
	sw	s3, 16(sp)
	sw	s4, 20(sp)
	sw	s5, 24(sp)
	sw	s6, 28(sp)

	/* Copy registers to preserved registers */
	move	s0, a0
	move	s1, a1
	move	s2, a2
	move	s3, a3
	MFC0(   s4, C0_Status )
	MFC0(   s5, C0_Config )
	MFC0_SEL_OPCODE( 22, R_C0_Config1, R_C0_SelConfig1 )     /* s6 = $22 */

	/* Disable interrupts */
	li	t0, ~M_StatusIE
	and	t0, s4, t0
	MTC0(   t0, C0_Status )
	
	/* Shift to uncached */
	la	t0, sys_cpu_icache_config_uncached
	KSEG1A( t0)
	jr	t0
	nop

sys_cpu_icache_config_uncached :
			       
	/* Enable write access to config1 */
	li	t0, C0_CONFIG_WC_BIT
	or	t0, s5, t0
	MTC0(	t0, C0_Config )

	/* Set Icache settings to reset values */
	li	t0, (M_Config1IS | M_Config1IL | M_Config1IA)
	and	t0, s3, t0
	li	t1, ~(M_Config1IS | M_Config1IL | M_Config1IA)
	and	t1, s6, t1
	or	t1, t0

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 9, R_C0_Config1, R_C0_SelConfig1 )   /* t1 = $9 */

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Prepare for initialising cache */
	
	/* a1 := line size (bytes) */
	la      a1, sys_icache_linesize
	lw	a1, 0(a1)

	/* a0 := cache size (bytes) */
	la      a0, sys_icache_lines
	lw	a0, 0(a0)
	multu	a0, a1
	mflo    a0

	/* Initialise */
	la	t0, sys_init_icache
	KSEG1A( t0)		/* Make it uncached */
	jal	t0
	nop

	/* Set Icache settings to requested values */
	li	t0, ~(M_Config1IS | M_Config1IL | M_Config1IA)
	and	t0, s6, t0

	li	t1, S_Config1IS
	sllv	t1, s0, t1
	or	t0, t1

	li	t1, S_Config1IL
	sllv	t1, s1, t1
	or	t0, t1

	li	t1, S_Config1IA
	sllv	t1, s2, t1
	or	t0, t1

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 8, R_C0_Config1, R_C0_SelConfig1 )    /* t0 = $8 */

	/* Disable write access to config1 */
	MTC0(	s5, C0_Config )

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Restore CP0 STATUS */
	MTC0(   s4, C0_Status )

	/* Return */
	lw	ra, 0(sp)
	lw	s0, 4(sp)
	lw	s1, 8(sp)
	lw	s2, 12(sp)
	lw	s3, 16(sp)
	lw	s4, 20(sp)
	lw	s5, 24(sp)
	lw	s6, 28(sp)

	jr	ra
	addiu	sp, 8*4

END( sys_cpu_icache_config )


		
/************************************************************************
 *
 *                          sys_cpu_dcache_config
 *  Description :
 *  -------------
 *
 *  Configure dcache
 *
 *  a0 holds the requested sets per way field
 *  a1 holds the requested line size (0 or hardware default) field
 *  a2 holds the requested associativity field
 *  a3 holds the reset value of CONFIG1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cpu_dcache_config )

	/* Reserve space on stack */
	addiu	sp, -8*4

	sw	ra, 0(sp)
	sw	s0, 4(sp)
	sw	s1, 8(sp)
	sw	s2, 12(sp)
	sw	s3, 16(sp)
	sw	s4, 20(sp)
	sw	s5, 24(sp)
	sw	s6, 28(sp)

	/* Copy registers to preserved registers */
	move	s0, a0
	move	s1, a1
	move	s2, a2
	move	s3, a3
	MFC0(   s4, C0_Status )
	MFC0(   s5, C0_Config )
	MFC0_SEL_OPCODE( 22, R_C0_Config1, R_C0_SelConfig1 )     /* s6 = $22 */
	
	/* Disable interrupts */
	li	t0, ~M_StatusIE
	and	t0, s4, t0
	MTC0(   t0, C0_Status )
		
	/* Flush D-Cache */
	addiu	sp, -4*4
	la      t0, sys_dcache_flush_all
	jal	t0
	nop
	addiu	sp, 4*4

	/* Shift to uncached */
	la	t0, sys_cpu_dcache_config_uncached
	KSEG1A( t0)
	jr	t0
	nop

sys_cpu_dcache_config_uncached :

	/* Enable write access to config1 */
	li	t0, C0_CONFIG_WC_BIT
	or	t0, s5, t0
	MTC0(	t0, C0_Config )

	/* Set Dcache settings to reset values */
	li	t0, (M_Config1DS | M_Config1DL | M_Config1DA)
	and	t1, s3, t0
	li	t0, ~(M_Config1DS | M_Config1DL | M_Config1DA)
	and	t2, s6, t0
	or	t2, t1

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 10, R_C0_Config1, R_C0_SelConfig1 )  /* t2 = $10 */

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Prepare for initialising cache */

	/* a2 := processor type */
	la	a2, sys_processor
	lw	a2, 0(a2)

	/* a1 := line size (bytes) */
	la      a1, sys_dcache_linesize
	lw	a1, 0(a1)

	/* a0 := cache size (bytes) */
	la      a0, sys_dcache_lines
	lw	a0, 0(a0)
	multu	a0, a1
	mflo    a0

	/* Initialise */
	la	t0, sys_init_dcache
	KSEG1A( t0)		/* Make it uncached */
	jal	t0
	nop
	
	/* Set Dcache settings to requested values */
	li	t0, ~(M_Config1DS | M_Config1DL | M_Config1DA)
	and	t0, s6, t0

	li	t1, S_Config1DS
	sllv	t1, s0, t1
	or	t0, t1

	li	t1, S_Config1DL
	sllv	t1, s1, t1
	or	t0, t1

	li	t1, S_Config1DA
	sllv	t1, s2, t1
	or	t0, t1

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 8, R_C0_Config1, R_C0_SelConfig1 )   /* t0 = $8 */

	/* Disable write access to config1 */
	MTC0(	s5, C0_Config )

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Restore CP0 STATUS */
	MTC0(   s4, C0_Status )

	/* Return */
	lw	ra, 0(sp)
	lw	s0, 4(sp)
	lw	s1, 8(sp)
	lw	s2, 12(sp)
	lw	s3, 16(sp)
	lw	s4, 20(sp)
	lw	s5, 24(sp)
	lw	s6, 28(sp)

	jr	ra
	addiu	sp, 8*4
	
END( sys_cpu_dcache_config )
		


/************************************************************************
 *
 *                          sys_cpu_mmu_config
 *  Description :
 *  -------------
 *
 *  Configure MMU
 *
 *  a0 holds the required setting of Config0[8]
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cpu_mmu_config )

	/* Disable interrupts (store old value of CP0 STATUS) */
	MFC0(   t0, C0_Status )
	li	t1, ~M_StatusIE
	and	t1, t0, t1
	MTC0(   t1, C0_Status )

	/* Enable write access to Config0[8] */
	MFC0(   t1, C0_Config )
	li	t2, C0_CONFIG_WC_BIT
	or	t1, t1, t2
	MTC0(	t1, C0_Config )

	/* Set bit 8 */
	li	t2, ~(1 << 8)
	and	t1, t2
	sll	a0, 8
	or	t1, a0
	MTC0(   t1, C0_Config )

	/* Disable write access to Config1[8] */
	li	t2, ~C0_CONFIG_WC_BIT
	and	t1, t2
	MTC0(   t1, C0_Config )	

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Restore CP0 STATUS */
	MTC0(   t0, C0_Status )

	/* Return */
	jr	ra
	nop
		
END( sys_cpu_mmu_config )



/************************************************************************
 *
 *                          sys_cpu_configurability
 *  Description :
 *  -------------
 *
 *  Determine cpu configurability
 *