info.c

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

			  sizeof(wdata_cur)) == OK) )
        {
            if(SHELL_PUTS( "DCACHE associativity =" )) return FALSE;

            if (wdata_cur == 1)
	        sprintf( msg, "direct mapped" );
	    else
   	        sprintf( msg, "%d-way", wdata_cur );

	    if( wdata != wdata_cur )
	    {
	        if( wdata == 1 )
	            sprintf( &msg[strlen(msg)], " (direct mapped)\n" );
	        else
	            sprintf( &msg[strlen(msg)], " (%d-way)\n", wdata );
	    }
	    else
	        sprintf( &msg[strlen(msg)], "\n" );

            if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
        }
    }

    /* Secondary CACHE SIZE */
    if( SYSCON_read( SYSCON_CPU_SCACHE_SIZE_CURRENT_ID, 
		     &wdata_cur, 
		     sizeof(wdata_cur)) == OK )
    {
        if(SHELL_PUTS( "SCACHE size =" )) return FALSE;
        sprintf( msg, "%d kByte\n", wdata_cur/1024 );
	if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
    
    /* Secondary LINESIZE */
    if( SYSCON_read( SYSCON_CPU_SCACHE_LINESIZE_CURRENT_ID, 
		     &wdata_cur, 
		     sizeof(wdata_cur)) == OK )
    {
        if(SHELL_PUTS( "SCACHE line size =" )) return FALSE;
        sprintf( msg, "%d bytes\n", wdata_cur );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* Secondary CACHE ASSOC */
    if( SYSCON_read( SYSCON_CPU_SCACHE_ASSOC_CURRENT_ID, 
		     &wdata_cur, 
		     sizeof(wdata_cur)) == OK )
    {
        if(SHELL_PUTS( "SCACHE associativity =" )) return FALSE;

        if (wdata_cur == 1)
	    sprintf( msg, "direct mapped\n" );
	else
   	    sprintf( msg, "%d-way\n", wdata_cur );

        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }


    /* TLB */
    if( (SYSCON_read( SYSCON_CPU_TLB_AVAIL_ID,
		 (void *)&tlb_avail,
		 sizeof(bool) ) == OK )		&&

        (SYSCON_read( SYSCON_CPU_TLB_COUNT_ID,
		     (void *)&bdata_cur,
		     sizeof(UINT8) ) == OK)     &&

        (SYSCON_read( SYSCON_CPU_TLB_COUNT_RESET_ID,
		     (void *)&bdata,
		     sizeof(UINT8) ) == OK) )
    {
        if(SHELL_PUTS( "TLB entries =" )) return FALSE;

	if( tlb_avail )
	{
	    sprintf( msg, "%d\n", bdata_cur );
	}
	else
	{
	    if( bdata != 0 )
	        sprintf( msg, "None (%d)\n", bdata );
	    else
	        strcpy( msg, "None\n" );
	}

        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
 
    if(SHELL_PUTS( "CPU type =")) return FALSE;   
    if(sys_mips32_64)
    {
        if(SHELL_PUTS_INDENT( 
	    sys_64bit ? "MIPS64\n" : "MIPS32\n", INDENT ))
	        return FALSE;

        if(SHELL_PUTS( "Architecture revision =" )) return FALSE;

	sprintf( msg, "%d\n", sys_arch_rev+1 );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
    else
    {
        if(SHELL_PUTS_INDENT( 
	    sys_64bit ? "64 Bit\n" : "32 Bit\n", INDENT )) 
	        return FALSE;
    }

    if(SHELL_PUTS( "MIPS16e implemented =")) return FALSE;
    if(SHELL_PUTS_INDENT( sys_mips16e ? "Yes\n" : "No\n", INDENT )) 
        return FALSE;

    if(SHELL_PUTS( "EJTAG implemented =")) return FALSE;
    if(SHELL_PUTS_INDENT( sys_ejtag  ? "Yes\n" : "No\n", INDENT )) 
        return FALSE;

    if(SHELL_PUTS( "FPU implemented =")) return FALSE;
    if(SHELL_PUTS_INDENT( sys_fpu    ? "Yes\n" : "No\n", INDENT )) 
        return FALSE;

    return TRUE;
}


/************************************************************************
 *                          info_cpu_boot
 ************************************************************************/
static bool
info_cpu_boot( void )
{
    char   msg[80];
    UINT32 wdata;
    bool   bdata;
    UINT32 cpu_freq, bus_freq;
    char   *s;

    if(SYSCON_read( SYSCON_CPU_CP0_PRID_ID, &wdata, sizeof(wdata)) == OK)
    {
        if( disp_prid( wdata ) )
	    return FALSE;
    }

    /* Endianess */
    if(SYSCON_read(SYSCON_CPU_ENDIAN_BIG_ID, &bdata, sizeof(bdata)) == OK)
    {
        if(SHELL_PUTS("Endianness =" )) return FALSE;
        if(SHELL_PUTS_INDENT( bdata ? "Big\n" : "Little\n", INDENT )) return FALSE;
    }

    /* CPU and bus frequency */
    if(
        (SYSCON_read( SYSCON_BOARD_CPU_CLOCK_FREQ_ID, 
		      &cpu_freq, sizeof(cpu_freq)) == OK) &&
	(SYSCON_read( SYSCON_BOARD_BUS_CLOCK_FREQ_ID, 
		      &bus_freq, sizeof(bus_freq)) == OK) )

    {
        if(SHELL_PUTS( "CPU/Bus frequency =" )) return FALSE;

        if( cpu_freq < 1000*10 )
            sprintf( msg, "%d Hz", cpu_freq );
        else if( cpu_freq < 1000000*10 )
            sprintf( msg, "%d kHz", (cpu_freq+500)/1000 );
        else
            sprintf( msg, "%d MHz", (cpu_freq+500000)/1000000 );

	s = &msg[strlen(msg)];

	if( bus_freq < 1000*10 )
            sprintf( s, " / %d Hz\n", bus_freq );
        else if( bus_freq < 1000000*10 )
            sprintf( s, " / %d kHz\n", (bus_freq+500)/1000 );
        else
            sprintf( s, " / %d MHz\n", (bus_freq+500000)/1000000 );

        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    return TRUE;
}


/************************************************************************
 *                          info_board
 ************************************************************************/
static bool
info_board( void )
{
    char       msg[80];
    UINT32     wdata;
    t_mac_addr mac;
    t_sn_ascii sn;
    char       *name;

    /* Base board type/revision */
    if(SYSCON_read(SYSCON_BOARD_PRODUCTID_ID, &wdata, sizeof(UINT32)) == OK)
    {
        if(SHELL_PUTS( "Board type/revision =" )) return FALSE;

	SYSCON_read( SYSCON_BOARD_PRODUCTNAME_ID, 
		     (void *)(&name),
		     sizeof(char *) );
	
	sprintf( msg, "0x%02x (%s)", wdata, name );
	
        if(SYSCON_read(SYSCON_BOARD_PRODUCTREV_ID, &wdata, sizeof(UINT32)) == OK)
        {
            sprintf( &msg[strlen(msg)], " / 0x%02x\n", wdata );
	}

        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* Platform specifics to be displayed */
    if( !shell_arch_info( INDENT ) )
        return FALSE;

    /* MAC address */
    if(SYSCON_read(SYSCON_COM_EN0_MAC_ADDR_ID, &mac, sizeof(mac)) == OK)
    {
	if(SHELL_PUTS( "MAC address =" )) return FALSE;

        sprintf( msg, "%02x.%02x.%02x.%02x.%02x.%02x\n",
	                 mac[0],
			 mac[1],
			 mac[2],
			 mac[3],
			 mac[4],
			 mac[5] );

        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* Serial number */
    if(SYSCON_read(SYSCON_BOARD_SN_ID, &sn, sizeof(sn)) == OK)
    {
	if(SHELL_PUTS( "Board S/N =" )) return FALSE;
	sprintf( msg, "%s\n", sn  );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* Determine bus frequency */
    if( SYSCON_read(
        SYSCON_BOARD_PCI_FREQ_KHZ_ID,
	(void *)&wdata,
	sizeof(UINT32) ) == OK )
    {
	if(SHELL_PUTS( "PCI bus frequency =" ) ) return FALSE;

	pci_busfreq_string( msg, wdata );
	strcat( msg, "\n" );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
  
    return TRUE;
}


/************************************************************************
 *                          info_sysctrl
 ************************************************************************/
static bool
info_sysctrl( void )
{
    char       msg[80];
    UINT32     wdata, minor, major;

    /* Platform specifics to be displayed */
    if( !shell_sysctrl_info( INDENT ) )
        return FALSE;

    /* Sysctrl Register window */
    if(SYSCON_read( SYSCON_SYSCTRL_REGADDR_BASE_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("Register base address =" )) return FALSE;
        sprintf( msg, "0x%08x\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* MSC01 system ID */
    if(SYSCON_read( SYSCON_SYSCTRL_SYSID_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("Sysid =" )) return FALSE;
        sprintf( msg, "0x%08x\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* MSC01 pbc revision */
    if(SYSCON_read( SYSCON_SYSCTRL_PBCREV_MAJOR_ID,
		    &major, sizeof(major)) == OK)
    {
        if(SHELL_PUTS("PBC rev. =" )) return FALSE;
        if(SYSCON_read( SYSCON_SYSCTRL_PBCREV_MINOR_ID,
		         &minor, sizeof(minor)) == OK)
            sprintf( msg, "%d.%d\n", major, minor );
        else
            sprintf( msg, "%d\n", major );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* MSC01 pci revision */
    if(SYSCON_read( SYSCON_SYSCTRL_PCIREV_MAJOR_ID,
		    &major, sizeof(major)) == OK)
    {
        if(SHELL_PUTS("PCI rev. =" )) return FALSE;
        if(SYSCON_read( SYSCON_SYSCTRL_PCIREV_MINOR_ID,
		         &minor, sizeof(minor)) == OK)
            sprintf( msg, "%d.%d\n", major, minor );
        else
            sprintf( msg, "%d\n", major );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* MSC01 "performance" bit */
    if(SYSCON_read( SYSCON_SYSCTRL_WC_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("Write coherency =" )) return FALSE;
        sprintf( msg, "%d\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* System RAM data width */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_FW_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM external width =" )) return FALSE;
        strcpy( msg, wdata == 1
                     ? ( sys_64bit ? "Full (64" : "Full (32" )
                     : ( sys_64bit ? "Half (32" : "Half (16" ) );
	strcat( msg, " bit)\n" );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* System RAM parity */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_PARITY_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM parity check =" )) return FALSE;
        strcpy( msg, wdata == 0 ? "No\n" : "Yes\n" );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* System RAM refresh interval */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_REFRESH_NS_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM refresh interval =" )) return FALSE;
        sprintf( msg, "%d ns\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* System RAM read delay */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_RDDEL_CYCLES_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM rddel =" )) return FALSE;
        sprintf( msg, "%d bus cycles\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

#if 0
    /* System RAM clock ratio */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_CLKRAT_CFG_ID,
		    &sdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM bus:ram clock ratio =" )) return FALSE;
        sprintf( msg, "%s\n", sdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
#endif

    /* CAS latency */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_CASLAT_CYCLES_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM CAS latency =" )) return FALSE;
	switch (wdata)
	{
	  case 5: strcpy( msg, "1.5 ram cycles\n" ); break;
	  case 6: strcpy( msg, "2.5 ram cycles\n" ); break;
          default: sprintf( msg, "%d ram cycles\n", wdata ); break;
	}
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* SRAS precharge */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_SRASPRCHG_CYCLES_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM min precharge delay =" )) return FALSE;
        sprintf( msg, "%d ram cycles\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* SRAS to SCAS delay */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_SRAS2SCAS_CYCLES_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM min RAS to CAS delay =" )) return FALSE;
        sprintf( msg, "%d ram cycles\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

#if 0
    /* System RAM CS delay */ 
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_CSLAT_CYCLES_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM Chip Select delay =" )) return FALSE;
        sprintf( msg, "%d ram cycles\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
#endif

    /* System RAM write latency */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_WRLAT_CYCLES_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM write latency =" )) return FALSE;
        sprintf( msg, "%d ram cycles\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }

    /* System RAM Write burst length */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_WRITE_BURSTLEN_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM write burst length =" )) return FALSE;
        sprintf( msg, "%d\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
 
    /* System RAM Write burst length */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_READ_BURSTLEN_CFG_ID,
		    &wdata, sizeof(wdata)) == OK)
    {
        if(SHELL_PUTS("SDRAM read burst length =" )) return FALSE;
        sprintf( msg, "%d\n", wdata );
        if(SHELL_PUTS_INDENT( msg, INDENT )) return FALSE;
    }
 
    return TRUE;
}
 

/************************************************************************
 *                          info_mem
 ************************************************************************/
static bool
info_mem( void )
{