dis.c

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

    UINT32  *addr )                 /* virtual address      */
{
    UINT32  inst;
    UINT32  op, funct, tf, rt, rs, sc, funct_bshfl,  /* Instruction fields   */
	    fr, ft, fs, fd,
            rd, r2, sa, code, base, 
            immediate, offset, index, 
            target, func,
            hint, hintx, sel, cc1, cc2,
	    lsb, msb,
            baddr, jaddr, hint10, rs21, bit6;
    t_opc   opc;

    if( (*addr) & 0x3 )
    {
        sprintf( dest,
                 "You can only disassemble from 32 bit boundaries.\n");
        return FALSE;
    };

    inst = REG32(*addr);
 
    dest    += sprintf(dest, "%08X:  %08X  ", *addr, inst);
    (*addr) += 4;
        
    /* Isolate all instruction fields */
    op          = (inst >> 26) & 0x3f;
    funct       = (inst >>  0) & 0x3f;
    tf          = (inst >> 16) & 0x01;
    rt          = (inst >> 16) & 0x1f;
    rs          = (inst >> 21) & 0x1f;
    rs21	= rs           & 0x01;
    funct_bshfl = (inst >>  6) & 0x1f;
    sc		= (inst >>  5) & 0x01;
    hint10	= (inst >> 10) & 0x01;
    bit6	= (inst >>  6) & 0x01;

    switch( op )
    {
      case 0 : /* SPECIAL */ 
        switch( funct )
	{
	  case 0  : 
	    switch(inst)
	    {
	      case 0        : opc = opc_nop;   break;
	      case 0x1 << 6 : opc = opc_ssnop; break;
	      case 0x3 << 6 : opc = opc_ehb;   break;
	      default       : opc = opc_sll;   break;
	    }
	    break;
	  case 1 : 
	    opc = movci[tf];
	    break;
	  case 2 :
	    opc = srl[rs21];
	    break;
	  case 6 :
	    opc = srlv[bit6];
	    break;
	  case 8 :
	    opc = jr[hint10];
	    break;
	  case 9 :
	    opc = jalr[hint10];
	    break;
	  default : 
	    opc = special[funct];
	    break;
	}
        break;
      case 1 : /* REGIMM */
        opc = regimm[rt];
        break;
      case 16 : /* COP0 */
        if( rs == 11 )
	    opc = mfmc0[sc];
	else
            opc = ( rs < 16 ) ? cop0[rs] : cop0co[funct];
        break;
      case 17 : /* COP1 */
        switch( rs )
        {
          case 8 :
            opc = bc1[rt & 0x3];
            break;
          case 9 :
            opc = bc1any2[tf];
            break;
          case 10 :
            opc = bc1any4[tf];
            break;
          case 16 :
            opc = (funct == 17) ? movcfs[tf] : cop1s[funct];
            break;
          case 17 :
            opc = (funct == 17) ? movcfd[tf] : cop1d[funct];
            break;
          case 20 :
            opc = cop1w[funct];
            break;
          case 21 :
            opc = cop1l[funct];
            break;
          case 22 :
            opc = (funct == 17) ? movcfps[tf] : cop1ps[funct];
            break;
          default :
            opc = cop1[rs];
            break;
        }
        break;
      case 18 : /* COP2 */
        opc = (rs == 8) ? bc2[rt & 0x3] : cop2[rs];
	break;
      case 19 : /* COP1X */
        opc = cop1x[funct];
        break;
      case 28 : /* SPECIAL2 */
        opc = special2[funct];
        break;
      case 31 : /* SPECIAL3 (release2) */
        opc = ( funct == 32 ) ? bshfl[funct_bshfl] : special3[funct];
	break;
      default :
        opc = opcode[op];
        break;
    }

    dest += sprintf(dest, "%-12s", (opc.type == 0) ? "rsvd" : opc.name);

    fr        = (inst >> 21) & 0x1f;
    ft        = (inst >> 16) & 0x1f;
    fs        = (inst >> 11) & 0x1f;
    fd        = (inst >> 6)  & 0x1f;
    rd        = (inst >> 11) & 0x1f;
    r2        = (inst >> 16) & 0x1f;
    sa        = (inst >> 6)  & 0x1f;
    code      = (inst >> 6)  & 0xfffff;
    base      = (inst >> 21) & 0x1f;
    immediate = (inst >> 0)  & 0xffff;
    offset    = SIGN( (inst >> 0)  & 0xffff, 16);
    index     = (inst >> 16) & 0x1f;
    target    = (inst >> 0)  & 0x3ffffff;
    func      = (inst >> 0)  & 0x1ffffff;
    op        = (inst >> 16) & 0x1f;
    hint      = (inst >> 16) & 0x1f;
    hintx     = (inst >> 11) & 0x1f;
    sel       = (inst >> 0)  & 0x7;
    cc1       = (inst >> 18) & 0x7;
    cc2       = (inst >> 8)  & 0x7;
    lsb	      = (inst >> 6)  & 0x1f;
    msb       = ((inst >> 11) & 0x1f);

    baddr     = (INT32)(*addr) + 4 * SIGN(immediate,16);
    jaddr     = (target<<2) | ((*addr) & 0xf0000000);

    switch (opc.type) 
    {
      case 0  : /* rsvd */
        break;
      case 1  : /* rd, rs, rt */
        sprintf(dest, "%s,%s,%s", regs[rd], regs[rs], regs[rt] );
        break;
      case 2  : /* fs, index(base) */
        sprintf(dest, "%s,%s(%s)", fpregs[fs], regs[index], regs[base]);
        break;
      case 3  : /* rt, rs, immediate (signed) */
        sprintf(dest, "%s,%s,%d", regs[rt], regs[rs], (INT16)immediate);
        break;
      case 4  : /* rs, immediate (signed) */
        sprintf(dest, "%s,%d", regs[rs], (INT16)immediate );
        break;
      case 5  : /* fd, fs, ft, rs */
        sprintf(dest, "%s,%s,%s,%s", fpregs[fd], fpregs[fs], fpregs[ft], regs[rs] );
        break;
      case 6  : /* cc1, baddr */
        sprintf(dest, "%d,0x%08x", cc1, baddr);
        break;
      case 7  : /* rs, rt, baddr */
        sprintf(dest, "%s,%s,0x%08x", regs[rs], regs[rt], baddr);
        break;
      case 8  : /* rs, baddr */
        sprintf(dest, "%s,0x%08x", regs[rs], baddr);
        break;
      case 9  : /* code */
        sprintf(dest, "0x%x", code );
        break;
      case 10 : /* cc2, fs, ft */
        sprintf(dest, "%d,%s,%s", cc2, fpregs[fs], fpregs[ft] );
        break;
      case 11 : /* 0xrt, offset(base) */
        sprintf(dest, "0x%x,%d(%s)", rt, offset, regs[base] );
        break;
      case 12 : /* rt, fs */
        sprintf(dest, "%s,%s", regs[rt], fpregs[fs] );
        break;
      case 13 : /* rd, rs */
        sprintf(dest, "%s,%s", regs[rd], regs[rs] );
        break;
      case 14 : /* func */
        sprintf(dest,"0x%x", func );
        break;
      case 15  : /* rt, rs, immediate (unsigned) */
        sprintf(dest, "%s,%s,0x%x", regs[rt], regs[rs], immediate);
        break;
      case 16 : /* fd, fs */
        sprintf(dest, "%s,%s", fpregs[fd], fpregs[fs] );
        break;
      case 17 : /* rs, rt */
        sprintf(dest, "%s,%s", regs[rs], regs[rt] );
        break;
      case 18 : /* Nothing further */
        break;
      case 19 : /* fd, fs, ft */
        sprintf(dest, "%s,%s,%s", fpregs[fd], fpregs[fs], fpregs[ft] );
        break;
      case 20 : /* rt, cp0(rd,sel) */
        sprintf(dest, "%s,%s", regs[rt], cp0regs[sel][rd] );
        break;
      case 21 : /* rd, rt, sa */
        sprintf(dest, "%s,%s,0x%x", regs[rd], regs[rt], sa );
        break;
      case 22 : /* rd, rt, rs */
        sprintf(dest, "%s,%s,%s", regs[rd], regs[rt], regs[rs] );
        break;
      case 23 : /* target */
        sprintf(dest, "0x%08x", jaddr );
        break;
      case 24 : /* rs */
        sprintf(dest, "%s", regs[rs] );
        break;
      case 25 : /* rt, offset(base) */
        sprintf(dest, "%s,%d(%s)", regs[rt], offset, regs[base] );
        break;
      case 26 : /* ft, offset(base) */
        sprintf(dest, "%s,%d(%s)", fpregs[ft], offset, regs[base] );
        break;
      case 27 : /* fd, index(base) */
        sprintf(dest, "%s,%s(%s)", fpregs[fd], regs[index], regs[base] );
        break;
      case 28 : /* rt, immediate */
        sprintf(dest, "%s,0x%x", regs[rt], immediate );
        break;
      case 29 : /* cop2reg, offset(base) */
        sprintf(dest, "$%d,%d(%s)", r2, offset, regs[base] );
        break;
      case 30 : /* fd, fr, fs, ft */
        sprintf(dest, "%s,%s,%s,%s", fpregs[fd], fpregs[fr], fpregs[fs], fpregs[ft] );
        break;
      case 31 : /* hintx, index(base) */
        sprintf(dest, "%d,%s(%s)", hintx, regs[index], regs[base] );
        break;
      case 32 : /* rd */
        sprintf(dest, "%s", regs[rd] );
        break;
      case 33 : /* rd, rs, cc1 */
        sprintf(dest, "%s,%s,%d", regs[rd], regs[rs], cc1 );
        break;
      case 34 : /* fd, fs, cc1 */
        sprintf(dest, "%s,%s,%d", fpregs[fd], fpregs[fs], cc1 );
        break;
      case 35 : /* fd, fs, rt */
        sprintf(dest, "%s,%s,%s", fpregs[fd], fpregs[fs], regs[rt] );
        break;
      case 36 : /* hint, offset(base) */
        sprintf(dest, "%d,%d(%s)", hint, offset, regs[base] );
        break;
      case 37 : /* rt, fp_control_reg */
        sprintf(dest, "%s,$%d", regs[rt], fs);
        break;
      case 38 : /* rt, rs, pos, size */ /* pos=lsb, size=msb+1 */
        sprintf(dest, "%s,%s,%d,%d", regs[rt], regs[rs], lsb, msb+1);
	break;
      case 39 : /* rt, rs, pos, size */ /* pos=lsb, size=msb-lsb+1 (may be negative !) */
        sprintf(dest, "%s,%s,%d,%d", regs[rt], regs[rs], lsb, msb-lsb+1);
	break;
      case 40 : /* rt, rd */
        sprintf(dest, "%s,%s", regs[rt], regs[rd]);
        break;
      case 41 : /* rd, rt */
        sprintf(dest, "%s,%s", regs[rd], regs[rt]);
        break;
      case 42 : /* offset(base) */
        sprintf(dest, "%d(%s)", offset, regs[base] );
        break;
      case 43 : /* rt (unless zero) */
        if(rt)
	    sprintf(dest, "%s", regs[rt]);
        break;
      case 44 : /* rt, 0xrd, sel (rd,sel is actually impl. specific) */
        sprintf(dest, "%s,0x%x,%d", regs[rt], rd, sel );
        break;
      case 45 : /* rt, 0xrd (rd,sel is actually impl. specific) */
        sprintf(dest, "%s,0x%x", regs[rt], rd );
	break;
      default : /* Never happens */
        break;
    }

    strcat( dest, "\n" );

    return TRUE;
}

/************************************************************************
 *                          disassemble16
 ************************************************************************/
static bool
disassemble16(
    char    *dest,				  /* destination line   */
    UINT32  *addr )				  /* virtual address    */
{
    UINT32  inst;
    UINT32  op;
    bool    extend;
    t_opc   opc;
    UINT32  x, f, f4, s, funct8, funct, ry;   /* Instruction fields	*/
    UINT32  count;
    
    if( (*addr) & 0x1 ) 
    {
        sprintf( dest,
                 "You can only disassemble from 16 bit boundaries.\n");
        return FALSE;
    };

    inst   = (UINT32)REG16(*addr);
    op     = (inst >> 11) & 0x1f;
    extend = ( op == 30 );

    if( extend || (op == 3) ) /* extend or jal(x) */
    {
	/* Setup the extended instrution */
	inst = (inst << 16) | (UINT32)REG16(*addr + 2);

        dest += sprintf(dest, "%08X:  %08X  ", *addr, inst);

        (*addr) += 4;

        if( extend )
            op = (inst >> 11) & 0x1f;
    }
    else
    {
        dest    += sprintf(dest, "%08X:  %04X      ", *addr, inst);
        (*addr) += 2;
    }

    /* Isolate all instruction fields */
    x      = (inst >> 26) & 0x01;
    f      = (inst >> 0 ) & 0x03;
    f4     = (inst >> 4)  & 0x01;
    funct8 = (inst >> 8)  & 0x07;
    s      = (inst >> 7)  & 0x01;
    funct  = (inst >> 0)  & 0x1f;
    ry     = (inst >> 5)  & 0x7;

    switch( op )
    {
      case 3 :  /* JALX */ 
        opc = opc16_jalx[x]; 
        break;
      case 6 :  /* SHIFT */
        opc = opc16_shift[f];
        break;
      case 8 :  /* RRI-A */
        opc = opc16_rria[f4];
        break;
      case 12 : /* I8 */
        opc = (funct8 == 4) ? opc16_svrs[s] : opc16_i8[funct8];
        break;
      case 28 : /* RRR */
	opc = extend ? opc16_asmacro : opc16_rrr[f];
        break;
      case 29 : /* RR */
        switch( funct )
        {
          case 0  : opc = opc16_jalrc[ry]; break;
          case 17 : opc = opc16_cnvt[ry];  break;
          default : opc = opc16_rr[funct]; break;
        }
        break;
      case 31 : /* I64 */
        opc = opc16_i64[funct8];
        break;
      default :
        opc = opc16[op];
        break;
    }

    /* Assembler alias */
    if( inst == MIPS16E_OPCODE_NOP ) 
        opc = opc16_nop;

    dest += sprintf( dest, "%-12s", (opc.type == 0xff) ? "rsvd" : opc.name );

    switch (opc.type) 
    {
      case 0 : /* No parameters */
        break;
      case 1 :
        if( extend )
            sprintf(dest, "%s,sp,%d", 
			  regs16[IMM(inst,10,8)], 
			  SIGN(
			       (IMM(inst,20,16) << 11) |
			       (IMM(inst,26,21) << 5 ) |
			       (IMM(inst, 4, 0) << 0 ),
			       16 ) );
	else
            sprintf(dest, "%s,sp,%d", 
			  regs16[IMM(inst,10,8)], 
			  IMM(inst,7,0) << 2 );
	break;
      case 2 :
        if( extend )
            sprintf(dest, "%s,pc,%d", 
			  regs16[IMM(inst,10,8)], 
			  SIGN(
			       (IMM(inst,20,16) << 11) |
			       (IMM(inst,26,21) << 5 ) |
			       (IMM(inst, 4, 0) << 0 ),
			       16 ) );
	else
            sprintf(dest, "%s,pc,%d", 
			  regs16[IMM(inst,10,8)], 
			  IMM(inst,7,0) << 2 );
	break;
      case 3 :
        if( extend )
	    sprintf(dest, "0x%08x",
			  (INT32)(*addr) +
			  SIGN( 
			       ( (IMM(inst,20,16) << 11) |
			         (IMM(inst,26,21) << 5 ) |
			         (IMM(inst, 4, 0) << 0 ) ) << 1,
				 17 ) );
	else
	    sprintf(dest, "0x%08x",
			  (INT32)(*addr) +
			  SIGN( 
			      IMM(inst,10,0) << 1, 
			      12 ) );
	break;
      case 4 :
        if( extend )
	    sprintf(dest, "%s,0x%08x",
			  regs16[IMM(inst,10,8)], 
			  (INT32)(*addr) +
			  SIGN( 
			       ( (IMM(inst,20,16) << 11) |
			         (IMM(inst,26,21) << 5 ) |
			         (IMM(inst, 4, 0) << 0 ) ) << 1,
				 17 ) );
	else
	    sprintf(dest, "%s,0x%08x",
			  regs16[IMM(inst,10,8)], 
			  (INT32)(*addr) +
			  SIGN( 
			      IMM(inst,7,0) << 1, 
			      9 ) );
	break;