dis.c

MIPS YAMON, a famous monitor inc. source, make file and PDF manuals.

/************************************************************************
 *
 *  dis.c
 *
 *  Monitor command for disassembling an address range
 *
 *  Disassembles MIPS64/MIPS32 instructions.
 *  Includes MIPS-3D(TM) and MIPS16e(TM) ASEs.
 *
 *  dis [-m] [-16] <address> [<count>]
 *
 * ######################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
 * this code does not give recipient any license to any intellectual
 * property rights, including any patent rights, that cover this code.
 *
 * This code shall not be exported, reexported, transferred, or released,
 * directly or indirectly, in violation of the law of any country or
 * international law, regulation, treaty, Executive Order, statute,
 * amendments or supplements thereto. Should a conflict arise regarding the
 * export, reexport, transfer, or release of this code, the laws of the
 * United States of America shall be the governing law.
 *
 * This code constitutes one or more of the following: commercial computer
 * software, commercial computer software documentation or other commercial
 * items. If the user of this code, or any related documentation of any
 * kind, including related technical data or manuals, is an agency,
 * department, or other entity of the United States government
 * ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this code, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
 * of this code by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms
 * and conditions covering this code from MIPS Technologies or an authorized
 * third party.
 *
 *
 *
 * 
 * mips_end_of_legal_notice
 * 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <sys_api.h>
#include <string.h>
#include <stdio.h>
#include <ctype.h>
#include <shell_api.h>
#include <shell.h>
#include <mips.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

typedef struct
{
    UINT8 type;
    char *name;
}
t_opc;

#define DIS_DEFAULT_COUNT    16

#define IMM( n, msb, lsb )   (((n) >> (lsb)) & MSK((msb)-(lsb)+1))
#define ZERO2EIGHT( n )	     (((n) == 0) ? 8 : (n))
#define ZERO2_128( n )	     (((n) == 0) ? 128 : (n))
#define SIGN( n, bits )      ( (n) |\
		                   (((n) & (1 << ((bits) - 1))) ?\
				       (MSK(32-(bits)) << (bits)) : 0))

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/* OPTIONS */
static t_cmd_option options[] =
{ 
#define OPTION_MORE	0
  { "m",  "Prompt user for keypress after each screen of data" },
#define OPTION_MIPS16E  1
  { "16", "Disassemble MIPS16e code" }
};
#define OPTION_COUNT	(sizeof(options)/sizeof(t_cmd_option))

/* Options */
static bool   more;
static UINT32 address, count;
static bool   mips16e;
static UINT32 rc = OK;

/************************************************************************
 *  Static variables - Opcode and register tables
 ************************************************************************/

/************************************************************************
 *		    MIPS64/32, MIPS-3D ASE
 ************************************************************************/

/* Encoding of opcode field (31..26) */
static t_opc opcode[64] = {
  {0,  ""     }, {0,  ""      }, {23, "j"    }, {23, "jal"  },
  {7,  "beq"  }, {7,  "bne"   }, {8,  "blez" }, {8,  "bgtz" },
  {3,  "addi" }, {3,  "addiu" }, {3,  "slti" }, {3,  "sltiu"},
  {15, "andi" }, {15, "ori"   }, {15, "xori" }, {28, "lui"  },
  {0,  ""     }, {0,  ""      }, {14, "cop2" }, {0,  ""     },
  {7,  "beql" }, {7,  "bnel"  }, {8,  "blezl"}, {8,  "bgtzl"},
  {3,  "daddi"}, {3,  "daddiu"}, {25, "ldl"  }, {25, "ldr"  },
  {0,  ""     }, {23, "jalx"  }, {18, "mdmx" }, {0,  ""     },
  {25, "lb"   }, {25, "lh"    }, {25, "lwl"  }, {25, "lw"   },
  {25, "lbu"  }, {25, "lhu"   }, {25, "lwr"  }, {25, "lwu"  },
  {25, "sb"   }, {25, "sh"    }, {25, "swl"  }, {25, "sw"   },
  {25, "sdl"  }, {25, "sdr"   }, {25, "swr"  }, {11, "cache"},
  {25, "ll"   }, {26, "lwc1"  }, {29, "lwc2" }, {36, "pref" },
  {25, "lld"  }, {26, "ldc1"  }, {29, "ldc2" }, {25, "ld"   },
  {25, "sc"   }, {26, "swc1"  }, {29, "swc2" }, {0,  ""     },
  {25, "scd"  }, {26, "sdc1"  }, {29, "sdc2" }, {25, "sd"   }
};

/*  SPECIAL opcode (opcode field = 0). 
 *  Encoding of function field (5..0)  
 */
static t_opc special[64] = {
  {0,  ""       }, {0,  ""      }, {0,  ""      }, {21, "sra"   },
  {22, "sllv"   }, {0,  ""      }, {0,  ""      }, {22, "srav"  },
  {0,  ""       }, {0,  ""      }, {1,  "movz"  }, {1,  "movn"  },
  {9,  "syscall"}, {9,  "break" }, {0,  ""      }, {18, "sync"  },
  {32, "mfhi"   }, {24, "mthi"  }, {32, "mflo"  }, {24, "mtlo"  },
  {22, "dsllv"  }, {0,  ""      }, {22, "dsrlv" }, {22, "dsrav" },
  {17, "mult"   }, {17, "multu" }, {17, "div"   }, {17, "divu"  },
  {17, "dmult"  }, {17, "dmultu"}, {17, "ddiv"  }, {17, "ddivu" },
  {1,  "add"    }, {1,  "addu"  }, {1,  "sub"   }, {1,  "subu"  },
  {1,  "and"    }, {1,  "or"    }, {1,  "xor"   }, {1,  "nor"   },
  {0,  ""       }, {0,  ""      }, {1,  "slt"   }, {1,  "sltu"  },
  {1,  "dadd"   }, {1,  "daddu" }, {1,  "dsub"  }, {1,  "dsubu" },
  {17, "tge"    }, {17, "tgeu"  }, {17, "tlt"   }, {17, "tltu"  },
  {17, "teq"    }, {0,  ""      }, {17, "tne"   }, {0,  ""      },
  {21, "dsll"   }, {0,  ""      }, {21, "dsrl"  }, {21, "dsra"  },
  {21, "dsll32" }, {0,  ""      }, {21, "dsrl32"}, {21, "dsra32"}
};

/*  jr,jalr,srl,srlv (SPECIAL opcode, functions = 2,6,8,9)
 */
static t_opc jr[2] = {       /* Encoding of msb of hint field (bit 10) */
  {24, "jr"}, {24, "jr.hb"}
};

static t_opc jalr[2] = {     /* Encoding of msb of hint field (bit 10) */
  {13, "jalr"}, {13, "jalr.hb"}
};

static t_opc srl[2] = {      /* Encoding of bit 21 */
  {21, "srl"}, {21,"rotr"}
};

static t_opc srlv[2] = {     /* Encoding of bit 6 */
  {22, "srlv"}, {22, "rotrv"}
};

/*  REGIMM opcode (opcode field = 1). 
 *  Encoding of rt field (20..16) 
 */
static t_opc regimm[32] = {
  {8, "bltz"  }, {8, "bgez"  }, {8, "bltzl"  }, {8,  "bgezl"  },
  {0, ""      }, {0, ""      }, {0, ""       }, {0,  ""       },
  {4, "tgei"  }, {4, "tgeiu" }, {4, "tlti"   }, {4,  "tltiu"  },
  {4, "teqi"  }, {0, ""      }, {4, "tnei"   }, {0,  ""       },
  {8, "bltzal"}, {8, "bgezal"}, {8, "bltzall"}, {8,  "bgezall"},
  {0, ""      }, {0, ""      }, {0, ""       }, {0,  ""       },
  {0, ""      }, {0, ""      }, {0, ""       }, {0,  ""       },
  {0, ""      }, {0, ""      }, {0, ""       }, {42, "synci"  }
};

/*  SPECIAL2 opcode (opcode field = 28). 
 *  Encoding of function field (5..0)
 */
static t_opc special2[64] = {
  {17, "madd"}, {17, "maddu"}, {1,  "mul"}, {0,  ""     },
  {17, "msub"}, {17, "msubu"}, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  ""   }, {0,  ""     },
  {18, "UDI" }, {18, "UDI"  }, {18, "UDI"}, {18, "UDI"  },
  {18, "UDI" }, {18, "UDI"  }, {18, "UDI"}, {18, "UDI"  },
  {18, "UDI" }, {18, "UDI"  }, {18, "UDI"}, {18, "UDI"  },
  {18, "UDI" }, {18, "UDI"  }, {18, "UDI"}, {18, "UDI"  },
  {13, "clz" }, {13, "clo"  }, {0,  ""   }, {0,  ""     },
  {13, "dclz"}, {13, "dclo" }, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  ""   }, {0,  ""     },
  {0,  ""    }, {0,  ""     }, {0,  "",  }, {9,  "sdbbp"}
};

/*  SPECIAL3 opcode (opcode field = 31).
 *  MIPS32/64 Release 2 instructions.
 *  Encoding of function field (5..0)
 */
static t_opc special3[64] = {
  {38, "ext"}, {0,  ""}, {0, ""}, {0,  ""     },
  {39, "ins"}, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0, ""      },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     },
  {0,  ""   }, {0,  ""}, {0, ""}, {40, "rdhwr"},
  {0,  ""   }, {0,  ""}, {0, ""}, {0,  ""     }
};

/*  COP1X opcode (opcode field = 19). 
 *  Encoding of function field (5..0)
 */
static t_opc cop1x[64] = {
  {27, "lwxc1"  }, {27, "ldxc1"  }, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {27, "luxc1"  }, {0,  ""        }, {0,  ""     },
  {2,  "swxc1"  }, {2,  "sdxc1"  }, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {2,  "suxc1"  }, {0,  ""        }, {31, "prefx"},
  {0,  ""       }, {0,  ""       }, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {0,  ""       }, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {0,  ""       }, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {0,  ""       }, {5,  "alnv.ps" }, {0,  ""     },
  {30, "madd.s" }, {30, "madd.d" }, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {0,  ""       }, {30, "madd.ps" }, {0,  ""     },
  {30, "msub.s" }, {30, "msub.d" }, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {0,  ""       }, {30, "msub.ps" }, {0,  ""     },
  {30, "nmadd.s"}, {30, "nmadd.d"}, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {0,  ""       }, {30, "nmadd.ps"}, {0,  ""     },
  {30, "nmsub.s"}, {30, "nmsub.d"}, {0,  ""        }, {0,  ""     },
  {0,  ""       }, {0,  ""       }, {30, "nmsub.ps"}, {0,  ""     }
};

/*  MOVCI opcodes (SPECIAL opcode, function = 1)
 *  Encoding of tf field (bit 16)
 */
static t_opc movci[2] = {
  {33, "movf"}, {33, "movt"}
};

/*  COP0 opcode (opcode field = 16)
 *  Encoding of rs field (25..21) for rs < 16 
 */
static t_opc cop0[16] = {
  {20, "mfc0"}, {20, "dmfc0"}, {0,  ""},       {0, ""},
  {20, "mtc0"}, {20, "dmtc0"}, {0,  ""},       {0, ""},
  {0,  ""    }, {0,  ""     }, {41, "rdpgpr"}, {0, ""},
  {0,  ""    }, {0,  ""     }, {41, "wrpgpr"}, {0, ""}
};

/* COP0.MFMC0 opcodes (COP0 opcode, rs == 11)
 * Encoding of sc field (bit 5)
 */
static t_opc mfmc0[2] = {
  {43, "di"}, {43, "ei"}
};

/*  COP0 opcode (opcode field = 16)
 *  Encoding of function field (5..0) for rs >= 16
 */

static t_opc cop0co[64] = {
  {0,  ""    }, {18, "tlbr"}, {18, "tlbwi"}, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {18, "tlbwr"}, {0,  ""     },
  {18, "tlbp"}, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {18, "eret"}, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {18, "deret"},
  {18, "wait"}, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     },
  {0,  ""    }, {0,  ""    }, {0,  ""     }, {0,  ""     }
};

/*  COP1 opcode (opcode field = 17)
 *  Encoding of rs field (25..21) for rs < 16
 */
static t_opc cop1[16] = {
  {12, "mfc1"}, {12, "dmfc1"}, {37, "cfc1"}, {12, "mfhc1"},
  {12, "mtc1"}, {12, "dmtc1"}, {37, "ctc1"}, {12, "mthc1"},
  {0,  ""    }, {0,  ""     }, {0,  ""    }, {0,  ""},
  {0,  ""    }, {0,  ""     }, {0,  ""    }, {0,  ""}
}; 

/*  BC1 opcode (opcode field = 17) for rs = 8
 *  Encoding of rt field (17..16) 
 */
static t_opc bc1[4] = {
  {6, "bc1f" }, {6, "bc1t" },
  {6, "bc1fl"}, {6, "bc1tl"}
};

/*  BC1ANY2 opcodes (opcode field = 17) for rs = 9
 *  Encoding of tf field (bit 16)
 */
static t_opc bc1any2[2] = {
  {6, "bc1any2f"}, {6, "bc1any2t"}
};

/*  BC1ANY4 opcodes (opcode field = 17) for rs = 10
 *  Encoding of tf field (bit 16)
 */
static t_opc bc1any4[2] = {
  {6, "bc1any4f"}, {6, "bc1any4t"}
};

/*  COP1 opcode (opcode field = 17) for rs=16 (S) 
 *  Encoding of function field (5..0)
 */
static t_opc cop1s[64] = {
  {19, "add.s"    }, {19, "sub.s"    }, {19, "mul.s"    }, {19, "div.s"    },
  {16, "sqrt.s"   }, {16, "abs.s"    }, {16, "mov.s"    }, {16, "neg.s"	   },
  {16, "round.l.s"}, {16, "trunc.l.s"}, {16, "ceil.l.s" }, {16, "floor.l.s"},
  {16, "round.w.s"}, {16, "trunc.w.s"}, {16, "ceil.w.s" }, {16, "floor.w.s"},
  {0,  ""         }, {0,  ""         }, {35, "movz.s"   }, {35, "movn.s"   },
  {0,  ""         }, {16, "recip.s"  }, {16, "rsqrt.s"  }, {0,  ""	   },
  {0,  ""         }, {0,  ""         }, {0,  ""	        }, {0,  ""	   },
  {19, "recip2.s" }, {16, "recip1.s" }, {16, "rsqrt1.s" }, {19,  "rsqrt2.s"},
  {0,  ""         }, {16, "cvt.d.s"  }, {0,  ""	        }, {0,  ""         },
  {16, "cvt.w.s"  }, {16, "cvt.l.s"  }, {19,  "cvt.ps.s"}, {0,  ""         },
  {0,  ""         }, {0,  ""	     }, {0,  ""	        }, {0,  ""         },
  {0,  ""         }, {0,  ""	     }, {0,  ""         }, {0,  ""         },
  {10, "c.f.s"    }, {10, "c.un.s"   }, {10, "c.eq.s"   }, {10, "c.ueq.s"  },
  {10, "c.olt.s"  }, {10, "c.ult.s"  }, {10, "c.ole.s"  }, {10, "c.ule.s"  },
  {10, "c.sf.s"   }, {10, "c.ngle.s" }, {10, "c.seq.s"  }, {10, "c.ngl.s"  },
  {10, "c.lt.s"   }, {10, "c.nge.s"  }, {10, "c.le.s"   }, {10, "c.ngt.s"  }
};

/*  COP1 opcode (opcode field = 17) for rs=17 (D) 
 *  Encoding of function field (5..0)
 */
static t_opc cop1d[64] = {
  {19, "add.d"    }, {19, "sub.d"    }, {19, "mul.d"   }, {19, "div.d"    },
  {16, "sqrt.d"   }, {16, "abs.d"    }, {16, "mov.d"   }, {16, "neg.d"	  },
  {16, "round.l.d"}, {16, "trunc.l.d"}, {16, "ceil.l.d"}, {16, "floor.l.d"},
  {16, "round.w.d"}, {16, "trunc.w.d"}, {16, "ceil.w.d"}, {16, "floor.w.d"},
  {0,  ""         }, {0,  ""         }, {35, "movz.d"  }, {35, "movn.d"	  },
  {0,  ""         }, {16, "recip.d"  }, {16, "rsqrt.d" }, {0,  ""	  },
  {0,  ""	  }, {0,  ""	     }, {0,  ""        }, {0,  ""	  },
  {19, "recip2.d" }, {16, "recip1.d" }, {16, "rsqrt1.d"}, {19, "rsqrt2.d" },
  {16, "cvt.s.d"  }, {0,  ""	     }, {0,  ""        }, {0,  ""	  },
  {16, "cvt.w.d"  }, {16, "cvt.l.d"  }, {0,  ""	       }, {0,  ""	  },
  {0,  ""	  }, {0,  ""	     }, {0,  ""	       }, {0,  ""	  },
  {0,  ""	  }, {0,  ""	     }, {0,  ""	       }, {0,  ""	  },
  {10, "c.f.d"	  }, {10, "c.un.d"   }, {10, "c.eq.d"  }, {10, "c.ueq.d"  },
  {10, "c.olt.d"  }, {10, "c.ult.d"  }, {10, "c.ole.d" }, {10, "c.ule.d"  },
  {10, "c.sf.d"	  }, {10, "c.ngle.d" }, {10, "c.seq.d" }, {10, "c.ngl.d"  },
  {10, "c.lt.d"	  }, {10, "c.nge.d"  }, {10, "c.le.d"  }, {10, "c.ngt.d"  }
};

/*  COP1 opcode (opcode field = 17) for rs=20 (W)
 *  Encoding of function field (5..0)
 */
static t_opc cop1w[64] = {
  {0,  ""       }, {0,  ""       }, {0,  ""         }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {16, "cvt.s.w"}, {16, "cvt.d.w"}, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {16, "cvt.ps.pw"}, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""}
};

/*  COP1 opcode (opcode field = 17) for rs=21 (L)
 *  Encoding of function field (5..0)
 */
static t_opc cop1l[64] = {
  {0,  ""       }, {0,  ""       }, {0,  ""         }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {16, "cvt.s.l"}, {16, "cvt.d.l"}, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {16, "cvt.ps.pw"}, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""},
  {0,  ""       }, {0,  ""       }, {0,  ""	    }, {0, ""}
};

/*  COP1 opcode (opcode field = 17) for rs=22 (PS)
 *  Encoding of function field (5..0)
 */
static t_opc cop1ps[64] = {
  {19, "add.ps"   }, {19, "sub.ps"   }, {19, "mul.ps"   }, {0,  ""         },
  {0,  ""	  }, {16, "abs.ps"   }, {16, "mov.ps"   }, {16, "neg.ps"   },
  {0,  ""	  }, {0,  ""	     }, {0,  ""		}, {0,  ""	   },
  {0,  ""	  }, {0,  ""	     }, {0,  ""		}, {0,  ""	   },
  {0,  ""	  }, {0,  ""	     }, {35, "movz.ps"  }, {35, "movn.ps"  },
  {0,  ""	  }, {0,  ""	     }, {0,  ""		}, {0,  ""	   },
  {19, "addr.ps"  }, {0,  ""	     }, {19, "mulr.ps"  }, {0,  ""	   },
  {19, "recip2.ps"}, {16, "recip1.ps"}, {16, "rsqrt1.ps"}, {19, "rsqrt2.ps"},
  {16, "cvt.s.pu" }, {0,  ""	     }, {0,  ""		}, {0,  ""         },
  {16, "cvt.pw.ps"}, {0,  ""	     }, {0,  ""		}, {0,  ""	   },
  {16, "cvt.s.pl" }, {0,  ""	     }, {0,  ""		}, {0,  ""	   },
  {19, "pll.ps"   }, {19, "plu.ps"   }, {19, "pul.ps"	}, {19, "puu.ps"   },
  {10, "c.f.ps"	  }, {10, "c.un.ps"  }, {10, "c.eq.ps"  }, {10, "c.ueq.ps" },
  {10, "c.olt.ps" }, {10, "c.ult.ps" }, {10, "c.ole.ps" }, {10, "c.ule.ps" },
  {10, "c.sf.ps"  }, {10, "c.ngle.ps"}, {10, "c.seq.ps" }, {10, "c.ngl.ps" },