mycrt0.s

MIPS 虚存测试, 表明在裸机环境, 无OS,无LOADER时如何定位目标码,将虚存与相应的物理单元做比较.原创.

# for init_tlb, This code sets the stack pointer to CSI scratch PAD space

#define LEAF(name)\
  		.##text;\
  		.##globl	name;\
  		.##ent	name;\
name:

#ifdef __ghs__
#define END(name)\
  		.##end	name
#else
#define END(name)\
  		.##size name,.-name;\
  		.##end	name
#endif

#define MTC0(src, dst)       \
		nop;	     \
	        mtc0 src,dst;\
		nop;

#define MFC0(dst, src)       \
	  	mfc0 dst,src

#define C0_Index		$0
#define C0_Random		$1
#define C0_EntryLo0		$2
#define C0_EntryLo1		$3
#define C0_Context		$4
#define C0_PageMask		$5
#define C0_Wired		$6
#define C0_EntryHi		$10

#define CA_CPU_RESET_ALL			0x05C4	
#define CA_CPU_RESET_BIT			0x0560	

#define CPU_A_RESET		0//1			//0=enable, 1=disable
#define CPU_V_RESET		0//2			//0=enable, 2=disable
#define CPU_H_RESET		0//4			//0=enable, 4=disable
#define CPU_T_RESET		0//8			//0=enable, 8=disable
#define CA_CA_RESET			16
#define CA_SA_RESET			32

#define INTR_HW_ENABLE	0xFC00	//enbale hw0~5
#define INTR_HW_0x200		0x80		//R1 mode vector 0x200
#define STA_HI_BOOT_BEV	0x40
#define STA_KERNAL_ERL	0x04	
#define STA_KERNAL_EXL	0x02	

.set noreorder
.set noat
.extern main
.text 

.org 0x0180										//BE009180
gen_hdlr:
        nop
        mfc0 $a0, $13, 0    	// read cause register
        nop
        move $a1, $zero
        eret

.org 0x0200										//BE009200
int_hdlr:
         mfc0 $t0, $13, 0	  	// read cause register
         nop
         mfc0 $t1, $12, 0	  	// status
         lui  $t2, INTR_HW_ENABLE     // check for IP7~2 (h/w intr)
         and  $t3, $t0, $t1		//mask
         and  $t3, $t2, $t3		//intr happend?
         mfc0 $t4, $12, 1	  	// intctl
         beq  $t3, $zero, int_hdlr_ret	//no  
         mfc0 $t5, $12, 2	  	// srsctl
         eret
//         jal  _timer_int_hdlr	//call C routine
         nop
int_hdlr_ret:
         eret

.org 0x0400									//3. BE009400, Boot jumps here
connex:
        addi $a0, $zero, 0xf 		//4. read cpu id, 
        mfc0 $a1, $15, 1   			// load cp0_ebase register from MIPS into $a1
        nop
        and  $a0, $a1, $a0; 
				                      
        addi $a1, $zero, 2
        sll  $a2, $a0, $a1			//get a2=0/4/8/c
        
        addi $a1, $zero, 8
        sll  $a3, $a0, $a1			//get a3=0/0x100/0x200/0x300

				lui   $v0, 0xBE00				//5.set sp=fp, goes down
        ori   $v0, 0xF7E0
        sub   $v0, $v0, $a3			//sp=bp=BE00-07E0/06E0/05E0 for A/V/H/T
        move  $sp, $v0
        move  $s8, $sp 					//fp
                
        beq  $a0, $zero, audio_cpu		//6. Go each CPU
        add  $a0, $a0, -1
        beq  $a0, $zero, video_cpu
        add  $a0, $a0, -1
        beq  $a0, $zero, host_cpu
        add  $a0, $a0, -1
        beq  $a0, $zero, demux_cpu
        nop
        j self_loop
audio_cpu:
				addi $a3, $zero, CPU_A_RESET	//each CPU's reset bit
				beq  $a3, $zero, cont
				nop
        j bypass	
        nop
video_cpu:
				addi $a3, $zero, CPU_V_RESET
				beq  $a3, $zero, cont
				nop
        j bypass	
        nop
host_cpu:
				addi $a3, $zero, CPU_H_RESET
				beq  $a3, $zero, cont
				nop
        j bypass	
        nop
demux_cpu:
				addi $a3, $zero, CPU_T_RESET
				beq  $a3, $zero, cont
				nop
        j bypass	
        nop
        
bypass:  
				addi $a0, $zero, 0x400     	//7. send pass for disabled CPU
        sw	 $a3, 0($a0)			        
        lui  $a1, 0xBE00						//8. reset bypassed CPU - not used due to verilog 
        add  $a2, $a1, $a2
//        sw   $a3, CA_CPU_RESET_BIT($a2)		//reset CPU will cause verilog unknown MIPS state
				lui   $a2, 0xBE00
				lw    $t1, CA_CPU_RESET_ALL($a2)        
				nop
self_loop:													//9. incase
				j    self_loop
				nop

cont: 
				lui   $a2, 0xBE00						//10. read back reset reg, seems cannot be read
				nop
				lw    $t5, CA_CPU_RESET_ALL($a2)
        lui  $v1, 0xBE01						//11.set gp=BE010000, goes up, BE010000-8000=BE008000
        move  $28, $v1			
        lui   $a3, INTR_HW_0x200   	//12. turn on IV bit in Cause Register(use offset 0200 for intr)
        mtc0  $a3, $13, 0
        lui   $t0, 0xBE00
        ori   $t0, 0x9000
        mtc0  $t0, $15, 1 					//13. Set EBASE to 0xBE009000
        nop
        li		$t1, STA_KERNAL_ERL
//      addi	$t1, $zero, (INTR_HW_ENABLE | 1) 	//14. Status Reg, 1=IE
        mtc0  $t1, $12, 0					//BEV=0
				jal main									//15. jump to C main()
				nop
//status(12,0): 0000FC01 
//IntCtl(12,1): no chnage, VS=0
//Cause(13,0) : 00800000



.global sys_tlb_write
/************************************************************************
 *                          sys_tlb_write
 *  a0 = pointer to array of 5 words
 *  array[0] = index
 *  array[1] = pagemask
 *  array[2] = entryhi
 *  array[3] = entrylo0
 *  array[4] = entrylo1
 ************************************************************************/
LEAF(sys_tlb_write)

	lw    $t0, 0($a0)
	MTC0( $t0, C0_Index )

	lw    $t0, 4($a0)
	MTC0( $t0, C0_PageMask )

	lw    $t0, 8($a0)
	MTC0( $t0, C0_EntryHi )

	lw    $t0, 12($a0)
	MTC0( $t0, C0_EntryLo0 )

	lw    $t0, 16($a0)
	MTC0( $t0, C0_EntryLo1 )

	tlbwi

	jr    $ra
	nop
END(sys_tlb_write)

.global sys_tlb_read
/************************************************************************
 *                          sys_tlb_read
 *  a0 = index
 *  a1 = pointer to array of 5 words. They will be filled with the
 *       following data :
 *
 *  array[0] = pagemask
 *  array[1] = entryhi
 *  array[2] = entrylo0
 *  array[3] = entrylo1
 ************************************************************************/
LEAF(sys_tlb_read)

	MTC0( $a0, C0_Index )
	tlbr

	MFC0( $t0, C0_PageMask )
	sw    $t0, 0($a1)
	MFC0( $t0, C0_EntryHi )
	sw    $t0, 4($a1)
	MFC0( $t0, C0_EntryLo0 )
	sw    $t0, 8($a1)
	MFC0( $t0, C0_EntryLo1 )
	sw    $t0, 12($a1)

	jr    $ra
	nop
END(sys_tlb_read)