📄 equate.inc
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;=========================================================================
; File Name: EQUATE.INC
;-------------------------------------------------------------------------
; Global EQUATE listing/usage
;-------------------------------------------------------------------------
; Note: All MASK definitions are intended to be OR'ed with a register value
; to SET a bit and AND'ed with the complement of the MASK (~MASK) to
; CLEAR a bit.
;-------------------------------------------------------------------------
LOWER_4K: EQU 0 ; Lower 4K of EPROM
UPPER_4K: EQU 1000h ; Upper 4K of EPROM
MAX_RAM: EQU FFh ; MAX size of local SRAM
;-------------------------------------------------------------------------
; CY7C66000 I/O Register Equates (see [3] Table 6-1)
;-------------------------------------------------------------------------
REG_PORT_0: EQU 00h
REG_PORT_1: EQU 01h
REG_PORT_2: EQU 02h
REG_PORT_3: EQU 03h
REG_PORT_0_INT_ENABLE: EQU 04h
REG_PORT_1_INT_ENABLE: EQU 05h
REG_PORT_2_INT_ENABLE: EQU 06h
REG_PORT_3_INT_ENABLE: EQU 07h
REG_GPIO_CONFIG: EQU 08h
REG_HAPI_I2C_CONFIG: EQU 09h
REG_A_ADDRESS: EQU 10h
REG_EP_A0_COUNT: EQU 11h
REG_EP_A0_MODE: EQU 12h
REG_EP_A1_COUNT: EQU 13h
REG_EP_A1_MODE: EQU 14h
REG_EP_A2_COUNT: EQU 15h
REG_EP_A2_MODE: EQU 16h
REG_STAT_CTRL: EQU 1Fh
REG_GLOBAL_INT_ENABLE: EQU 20h
REG_EP_INT_ENABLE: EQU 21h
REG_TIMER_LSB: EQU 24h
REG_TIMER_MSB: EQU 25h
REG_WDT_CLEAR: EQU 26h
REG_I2C_STAT_CTRL: EQU 28h
REG_I2C_DATA: EQU 29h
REG_DAC_DATA: EQU 30h
REG_DAC_INT_ENABLE: EQU 31h
REG_DAC_INT_POLARITY: EQU 32h
REG_DAC_ISINK_0: EQU 38h
REG_DAC_ISINK_1: EQU 39h
REG_DAC_ISINK_2: EQU 3Ah
REG_DAC_ISINK_3: EQU 3Bh
REG_DAC_ISINK_4: EQU 3Ch
REG_DAC_ISINK_5: EQU 3Dh
REG_DAC_ISINK_6: EQU 3Eh
REG_DAC_ISINK_7: EQU 3Fh
REG_B_ADDRESS: EQU 40h
REG_EP_B0_COUNT: EQU 41h
REG_EP_B0_MODE: EQU 42h
REG_EP_B1_COUNT: EQU 43h
REG_EP_B1_MODE: EQU 44h
REG_CONNECT_STAT: EQU 48h ; set = connected
REG_PORT_ENABLE: EQU 49h ; set = enabled
REG_PORT_SPEED: EQU 4Ah ; set bits = low speed device
REG_PORT_CTRL_LOW: EQU 4Bh
REG_PORT_CTRL_UP: EQU 4Ch
REG_PORT_SUSPEND: EQU 4Dh ; set = suspended
REG_PORT_RESUME: EQU 4Eh ; set = resume detected
REG_PORT_FORCE_LOW1_4: EQU 51h
REG_PORT_FORCE_LOW5_7: EQU 52h
REG_TEST: EQU F0h
REG_POR_CONFIG: EQU F1h
REG_HUB_TEST: EQU F2h
REG_DEVICE_ID: EQU F3h
REG_MFG_ID: EQU F4h
REG_PROC_STAT: EQU FFh
;---------------------------------------
Port0: EQU 00h ; GPIO port registers
Port1: EQU 01h
Port2: EQU 02h
Port3: EQU 03h
GPIOMode: EQU 08h
AddressA: EQU 10h ; Address A registers
EndpointA0Count: EQU 11h
EndpointA0Mode: EQU 12h
EndpointA1Count: EQU 13h
EndpointA1Mode: EQU 14h
EndpointA2Count: EQU 15h
EndpointA2Mode: EQU 16h
USBControl: EQU 1Fh
GlobalInterrupt: EQU 20h ; Interrupt registers
EndpointInterrupt: EQU 21h
WatchDog: EQU 26h
AddressB: EQU 40h ; Address B registers
EndpointB0Count: EQU 41h
EndpointB0Mode: EQU 42h
EndpointB1Count: EQU 43h
EndpointB1Mode: EQU 44h
HubPortConnect: EQU 48h ; Hub registers
HubPortEnable: EQU 49h
HubPortSpeed: EQU 4Ah
HubPortForceLo: EQU 4Bh
HubPortForceHi: EQU 4Ch
HubPortSuspend: EQU 4Dh
HubPortResume: EQU 4Eh
HubPortSE0: EQU 4Fh
HubPortData: EQU 50h
HubPortForceLowLo: EQU 51h
HubPortForceLowHi: EQU 52h
ProcessorControl: EQU FFh
HubAddress: EQU AddressB
HubControlCount: EQU EndpointB0Count
HubControlMode: EQU EndpointB0Mode
HubChangeCount: EQU EndpointB1Count
HubChangeMode: EQU EndpointB1Mode
KBAddress: EQU AddressA
KBControlCount: EQU EndpointA0Count
KBControlMode: EQU EndpointA0Mode
KBReportCount: EQU EndpointA1Count
KBReportMode: EQU EndpointA1Mode
;
; (InEndpoint2)
;
KBReport2Count: EQU EndpointA2Count
KBReport2Mode: EQU EndpointA2Mode
;---------------------------------------
; I/O ports
Port0_Data: EQU 00h ; GPIO data port 0
Port1_Data: EQU 01h ; GPIO data port 1
Port2_Data: EQU 02h ; GPIO data port 2
Port3_Data: EQU 03h ; GPIO data port 3
Port0_Interrupt: EQU 04h ; Interrupt enable for port 0
Port1_Interrupt: EQU 05h ; Interrupt enable for port 1
Port2_Interrupt: EQU 06h ; Interrupt enable for port 2
Port3_Interrupt: EQU 07h ; Interrupt enable for port 3
GPIO_Config: EQU 08h ; General purpose I/O configuration
; USB ports
USB_Device_Address: EQU 10h ; USB device address assigned by host
EP_A0_Counter: EQU 11h ; Address A endpoint 0 counter
EP_A0_Mode: EQU 12h ; Address A endpoint 0 configuration
EP_A1_Counter: EQU 13h ; Address A endpoint 1 counter
EP_A1_Mode: EQU 14h ; Address A endpoint 1 configuration
EP_A2_Counter: EQU 15h ; Address A endpoint 2 counter
EP_A2_Mode: EQU 16h ; Address A endpoint 2 configuration
USB_Status_Control: EQU 1Fh ; USB upstream status and control
; control ports
Global_Interrupt: EQU 20h ; Global interrupt enable
Endpoint_Interrupt: EQU 21h ; USB endpoint interrupt enable
Timer_LSB: EQU 24h ; lower eight bits of timer
Timer_MSB: EQU 25h ; upper six bits of timer
Watchdog: EQU 26h ; clear watchdog Timer
; DAC port
DAC_Data: EQU 30h ; GPIO DAC
DAC_Interrupt: EQU 31h ; DAC interrupt enable
DAC_Interrupt_Polarity: EQU 32h ; DAC interrupt polarity
DAC_Isink: EQU 38h ; 4-bit sink current
DAC_Isink0: EQU 38h ; bit 0
DAC_Isink1: EQU 39h ; bit 1
DAC_Isink2: EQU 3Ah ; bit 2
DAC_Isink3: EQU 3Bh ; bit 3
DAC_Isink4: EQU 3Ch ; bit 4
DAC_Isink5: EQU 3Dh ; bit 5
DAC_Isink6: EQU 3Eh ; bit 6
DAC_Isink7: EQU 3Fh ; bit 7
; processor control port
Status_Control: EQU FFh ; Processor Status and Control
;-----------------------------------
PORT0_DATA_REG: EQU 00h ; GPIO data port 0
PORT1_DATA_REG: EQU 01h ; GPIO data port 1
PORT2_DATA_REG: EQU 02h ; GPIO data port 2
PORT3_DATA_REG: EQU 03h ; GPIO data port 3
PORT0_INTERRUPT_REG: EQU 04h ; Interrupt enable for port 0
PORT1_INTERRUPT_REG: EQU 05h ; Interrupt enable for port 1
PORT2_INTERRUPT_REG: EQU 06h ; Interrupt enable for port 2
PORT3_INTERRUPT_REG: EQU 07h ; Interrupt enable for port 3
GPIO_CONFIG_REG: EQU 08h ; General purpose I/O configuration
;
; GPIO configuration
; Two bits per port the driver mode for each 8-bit port:
; 00 resistive interrupt on falling edge
; 01 CMOS no interrupts
; 10 open drain interrupt on falling edge
; 11 open drain interrupt on rising edge
PORT0_CONFIG_MASK: EQU 3h ; configuration bits port 0
PORT1_CONFIG_MASK: EQU 0Ch ; configuration bits port 1
PORT2_CONFIG_MASK: EQU 30h ; configuration bits port 2
PORT3_CONFIG_MASK: EQU C0h ; configuration bits port 3
RESISTIVE_NEG: EQU FFh
CMOS_NONE: EQU AAh
OPENDRAIN_NEG: EQU 55h
OPENDRAIN_POS: EQU 00h
; USB ports
USB_DEVICE_ADDRESS_REG: EQU 10h ; USB device address assigned by host
ADDRESS_ENABLE_BIT: EQU 80h ; enable the device address
EP_A0_COUNTER_REG: EQU 11h ; Address A endpoint 0 counter
EP_A0_MODE_REG: EQU 12h ; Address A endpoint 0 configuration
EP_A1_COUNTER_REG: EQU 13h ; Address A endpoint 1 counter
EP_A1_MODE_REG: EQU 14h ; Address A endpoint 1 configuration
USB_STATUS_CONTROL_REG: EQU 1Fh ; USB upstream status and control
; control ports
GLOBAL_INTERRUPT_REG: EQU 20h ; Global interrupt enable
ENDPOINT_INTERRUPT_REG: EQU 21h ; USB endpoint interrupt enable
TIMER_LSB_REG: EQU 24h ; lower eight bits of timer
TIMER_MSB_REG: EQU 25h ; upper six bits of timer
WATCHDOG_REG: EQU 26h ; clear watchdog Timer
; DAC port
DAC_DATA_REG: EQU 30h ; GPIO DAC
DAC_INTERRUPT_REG: EQU 31h ; DAC interrupt enable
DAC_INTERRUPT_POLARITY_REG: EQU 32h ; DAC interrupt polarity
DAC_ISINK_REG: EQU 38h ; 4-bit sink current
DAC_ISINK0_REG: EQU 38h ; bit 0
DAC_ISINK1_REG: EQU 39h ; bit 1
DAC_ISINK2_REG: EQU 3Ah ; bit 2
DAC_ISINK3_REG: EQU 3Bh ; bit 3
DAC_ISINK4_REG: EQU 3Ch ; bit 4
DAC_ISINK5_REG: EQU 3Dh ; bit 5
DAC_ISINK6_REG: EQU 3Eh ; bit 6
DAC_ISINK7_REG: EQU 3Fh ; bit 7
; processor control port
STATUS_CONTROL_REG: EQU FFh ; Processor Status and Control
;------------------------------------------------------------------------
; Register specific bit masks
;------------------------------------------------------------------------
; Interrupt enable masks
; for REG_GLOBAL_INT_ENABLE
MASK_128US: EQU 02h
MASK_1024US: EQU 04h
MASK_HUB: EQU 08h
MASK_DAC: EQU 10h
MASK_GPIO: EQU 20h
MASK_I2C: EQU 40h
; for REG_EP_INT_ENABLE
MASK_EPA0: EQU 01h
MASK_EPA1: EQU 02h
MASK_EPA2: EQU 04h
MASK_EPB0: EQU 08h
MASK_EPB1: EQU 10h
; interrupts
BusResetInterruptMask: EQU 01h
Timer128usInterruptMask: EQU 02h
Timer1msInterruptMask: EQU 04h
HubInterruptMask: EQU 08h
DACInterruptMask: EQU 10h
GPIOInterruptMask: EQU 20h
HAPIInterruptMask: EQU 20h
I2CInterruptMask: EQU 40h
; for REG_EP_{}_MODE Endpoint Mode Register control Modes
; Both EP0 and EP1 mode registers
; Controls how the endpoint responds to USB bus traffic
MASK_MODE: EQU 00001111b ; mode[3:0] bits
;----------------------------------------------------------------
; applicable modes SETUP IN OUT
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