📄 led_blink.c
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#ifndef _REFERENCE
//*-----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*-----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : led_blink.c
//* Object : Led Blinking for the AT91DB01.
//* Translator : ARM Software Development Toolkit V2.11a
//*
//* Imported resources : None
//* Exported resources : main
//*
//* 1.0 26/11/97 JCZ : Creation
//* 2.0 21/10/98 JCZ : Clean up
//*-----------------------------------------------------------------------------
#include "includes.h" /* uC/OS interface */
/*----- Called Macro instructions definition -----*/
/* None */
/*----- Files to be included Definition -----*/
//#ifndef AT91_DEBUG_NONE
//#include <stdio.h>
//#endif
//#include "Include/std_c.h"
//*--------------
//* AT91 Register
//*--------------
#define at91_reg volatile INT32U
#define AT91_REG(x) (*(volatile unsigned int *)(x))
//*---------------
//* Boolean values
//*---------------
#define TRUE 1
#define FALSE 0
//#include "Include/pio.h"
/*---------------------------------------------*/
/* Parallel I/O Interface Structure Definition */
/*---------------------------------------------*/
typedef struct
{
at91_reg PIO_PER ; /* PIO Enable Register */
at91_reg PIO_PDR ; /* PIO Disable Register */
at91_reg PIO_PSR ; /* PIO Status Register */
at91_reg Reserved0 ;
at91_reg PIO_OER ; /* Output Enable Register */
at91_reg PIO_ODR ; /* Output Disable Register */
at91_reg PIO_OSR ; /* Output Status Register */
at91_reg Reserved1 ;
at91_reg PIO_IFER ; /* Input Filter Enable Register */
at91_reg PIO_IFDR ; /* Input Filter Disable Register */
at91_reg PIO_IFSR ; /* Input Filter Status Register */
at91_reg Reserved2 ;
at91_reg PIO_SODR ; /* Set Output Data Register */
at91_reg PIO_CODR ; /* Clear Output Data Register */
at91_reg PIO_ODSR ; /* Output Data Status Register */
at91_reg PIO_PDSR ; /* Pin Data Status Register */
at91_reg PIO_IER ; /* Interrupt Enable Register */
at91_reg PIO_IDR ; /* Interrupt Disable Register */
at91_reg PIO_IMR ; /* Interrupt Mask Register */
at91_reg PIO_ISR ; /* Interrupt Status Register */
} StructPIO ;
/*-----------------------------*/
/* PIO Handler type definition */
/*-----------------------------*/
//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, INT32U pio_mask ) ;
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
/* Number of PIO Controller */
#define NB_PIO_CTRL 1
/* Base Address */
#define PIO_BASE ((StructPIO *) 0xFFFF0000 )
/* Number of PIO Lines */
#define NB_PIO 32
/* Parallel I/O Bits Definition */
#define P0 (1<<0)
#define P1 (1<<1)
#define P2 (1<<2)
#define P3 (1<<3)
#define P4 (1<<4)
#define P5 (1<<5)
#define P6 (1<<6)
#define P7 (1<<7)
#define P8 (1<<8)
#define P9 (1<<9)
#define P10 (1<<10)
#define P11 (1<<11)
#define P12 (1<<12)
#define P13 (1<<13)
#define P14 (1<<14)
#define P15 (1<<15)
#define P16 (1<<16)
#define P17 (1<<17)
#define P18 (1<<18)
#define P19 (1<<19)
#define P20 (1<<20)
#define P21 (1<<21)
#define P22 (1<<22)
#define P23 (1<<23)
#define P24 (1<<24)
#define P25 (1<<25)
#define P26 (1<<26)
#define P27 (1<<27)
#define P28 (1<<28)
#define P29 (1<<29)
#define P30 (1<<30)
#define P31 (1<<31)
/* PIO Multiplexing Definition */
/* There is only one PIO Controller */
#define PIO_CTRL 0
#define PIO_TC0 PIO_CTRL
#define TCLK0 P0
#define TIOA0 P1
#define TIOB0 P2
#define PIN_TC0 (TIOA0|TIOB0|TCLK0)
#define PIO_TC1 PIO_CTRL
#define TCLK1 P3
#define TIOA1 P4
#define TIOB1 P5
#define PIN_TC1 (TIOA1|TIOB1|TCLK1)
#define PIO_TC2 PIO_CTRL
#define TCLK2 P6
#define TIOA2 P7
#define TIOB2 P8
#define PIN_TC2 (TIOA2|TIOB2|TCLK2)
#define PIO_EXT_IRQ PIO_CTRL
#define PIN_IRQ0 P9
#define PIN_IRQ1 P10
#define PIN_IRQ2 P11
#define PIN_FIQ P12
#define PIO_USART0 PIO_CTRL
#define SCK0 P13
#define TXD0 P14
#define RXD0 P15
#define PIN_USART0 (SCK0|TXD0|RXD0)
#define PIO_USART1 PIO_CTRL
#define SCK1 P20
#define TXD1 P21
#define RXD1 P22
#define PIN_USART1 (SCK1|TXD1|RXD1)
#define MCKO P25
#define CS2 P26
#define CS3 P27
#define CS4 P31
#define CS5 P30
#define CS6 P29
#define CS7 P28
//#include "Include/tc.h"
/*----------------------------*/
/* Timer Structure Definition */
/*----------------------------*/
typedef struct
{
at91_reg TC_CCR ; /* Control Register */
at91_reg TC_CMR ; /* Mode Register */
at91_reg Reserved0 ;
at91_reg Reserved1 ;
at91_reg TC_CV ; /* Counter value */
at91_reg TC_RA ; /* Register A */
at91_reg TC_RB ; /* Register B */
at91_reg TC_RC ; /* Register C */
at91_reg TC_SR ; /* Status Register */
at91_reg TC_IER ; /* Interrupt Enable Register */
at91_reg TC_IDR ; /* Interrupt Disable Register */
at91_reg TC_IMR ; /* Interrupt Mask Register */
at91_reg Reserved2 ;
at91_reg Reserved3 ;
at91_reg Reserved4 ;
at91_reg Reserved5 ;
} StructTC ;
#define NB_TC_CHANNEL 3
typedef struct
{
StructTC TC[NB_TC_CHANNEL] ;
at91_reg TC_BCR ; /* Block Control Register */
at91_reg TC_BMR ; /* Block Mode Register */
} StructTCBlock ;
/*------------------------------------------------*/
/* Timer Counter Control Register Bits Definition */
/*------------------------------------------------*/
#define CLKEN (1<<0)
#define CLKDIS (1<<1)
#define SWTRG (1<<2)
/*---------------------------------------------*/
/* Timer Counter Mode Register Bits Definition */
/*---------------------------------------------*/
/* Edges Definition */
#define EdgeNone ((INT32U)0)
#define RisingEdge ((INT32U)1)
#define FallingEdge ((INT32U)2)
#define BothEdge ((INT32U)3)
/* Output Control Definition */
#define OutputNone ((INT32U)0)
#define SetOutput ((INT32U)1)
#define ClearOutput ((INT32U)2)
#define ToggleOutput ((INT32U)3)
/* Clock Selection */
#define TCCLKS (7<<0)
#define TCMCK2 (0<<0)
#define TCMCK8 (1<<0)
#define TCMCK32 (2<<0)
#define TCMCK128 (3<<0)
#define TCMCK1024 (4<<0)
#define TCXc0 (5<<0)
#define TCXc1 (6<<0)
#define TCXc2 (7<<0)
/* Clock Inversion */
#define CLKI (1<<3)
/* Burst Signal Selection */
#define BURST (3<<4)
#define BurstNone (0<<4)
#define BurstXc0 (1<<4)
#define BurstXc1 (2<<4)
#define BurstXc2 (3<<4)
/* Capture Mode : Counter Clock Stopped with RB Loading */
#define LDBSTOP (1<<6)
/* Waveform Mode : Counter Clock Stopped with RC Compare */
#define CPCSTOP (1<<6)
/* Capture Mode : Counter Clock Disabled with RB Loading */
#define LDBDIS (1<<7)
/* Waveform Mode : Counter Clock Disabled with RC Compare */
#define CPCDIS (1<<7)
/* Capture Mode : External Trigger Edge Selection */
#define B_ETRGEDG 8
#define ETRGEDG (3<<B_ETRGEDG)
/* Waveform Mode : External Event Edge Selection */
#define B_EEVTEDG 8
#define EEVTEDG (3<<B_EEVTEDG)
/* Capture Mode : TIOA or TIOB External Trigger Selection */
#define ABETRG (1<<10)
/* Waveform Mode : External Event Selection */
#define B_EEVT 10
#define EEVT (3<<B_EEVT)
#define EEVTTiob (0<<B_EEVT)
#define EEVTXc0 (1<<B_EEVT)
#define EEVTXc1 (2<<B_EEVT)
#define EEVTXc2 (3<<B_EEVT)
/* Waveform Mode : Enable Trigger on External Event */
#define ENETRG (1<<12)
/* RC Compare Enable Trigger Enable */
#define CPCTRG (1<<14)
/* Mode Selection */
#define WAVE (1<<15)
#define CAPT (0<<15)
/* Capture Mode : RA Loading Selection */
#define B_LDRA 16
#define LDRA (3<<B_LDRA)
/* Waveform Mode : RA Compare Effect on TIOA */
#define B_ACPA 16
#define ACPA (3<<B_ACPA)
/* Capture Mode : RB Loading Selection */
#define B_LDRB 18
#define LDRB (3<<B_LDRB)
/* Waveform Mode : RC Compare Effect on TIOA */
#define B_ACPC 18
#define ACPC (3<<B_ACPC)
/* Waveform Mode : External Event Effect on TIOA */
#define B_AEEVT 20
#define AEEVT (3<<B_AEEVT)
/* Waveform Mode : Software Trigger Effect on TIOA */
#define B_ASWTRG 22
#define ASWTRG (3<<B_ASWTRG)
/* Waveform Mode : RB Compare Effect on TIOB */
#define B_BCPB 24
#define BCPB (3<<B_BCPB)
/* Waveform Mode : RC Compare Effect on TIOB */
#define B_BCPC 26
#define BCPC (3<<B_BCPC)
/* Waveform Mode : External Event Effect on TIOB */
#define B_BEEVT 28
#define BEEVT (3<<B_BEEVT)
/* Waveform Mode : Software Trigger Effect on TIOB */
#define B_BSWTRG 30
#define BSWTRG (((INT32U)3)<<B_BSWTRG)
/*-----------------------------------------------*/
/* Timer Counter Status Register Bits Definition */
/*-----------------------------------------------*/
/* Counter Overflow Status */
#define COVFS (1<<0)
/* Load Overrun Status */
#define LOVRS (1<<1)
/* RA Compare Status */
#define CPAS (1<<2)
/* RB Compare Status */
#define CPBS (1<<3)
/* RC Compare Status */
#define CPCS (1<<4)
/* RA Loading Status */
#define LDRAS (1<<5)
/* RB Loading Status */
#define LDRBS (1<<6)
/* External Trigger Status */
#define ETRGS (1<<7)
/* Clock Status */
#define CLKSTA (1<<16)
/* TIOA Mirror */
#define MTIOA (1<<17)
/* TIOB Status */
#define MTIOB (1<<18)
/*------------------------------------------------------*/
/* Timer Counter Block Control Register Bits Definition */
/*------------------------------------------------------*/
/* Synchronisation Trigger */
#define TCSYNC 1
/*---------------------------------------------------*/
/* Timer Counter Block Mode Register Bits Definition */
/*---------------------------------------------------*/
#define B_TC0XC0S 0
#define TC0XC0S (3<<B_TC0XC0S)
#define TCLK0XC0 (0<<B_TC0XC0S)
#define NONEXC0 (1<<B_TC0XC0S)
#define TIOA1XC0 (2<<B_TC0XC0S)
#define TIOA2XC0 (3<<B_TC0XC0S)
#define B_TC1XC1S 2
#define TC1XC1S (3<<B_TC1XC1S)
#define TCLK1XC1 (0<<B_TC1XC1S)
#define NONEXC1 (1<<B_TC1XC1S)
#define TIOA0XC1 (2<<B_TC1XC1S)
#define TIOA2XC1 (3<<B_TC1XC1S)
#define B_TC2XC2S 4
#define TC2XC2S (3<<B_TC2XC2S)
#define TCLK2XC2 (0<<B_TC2XC2S)
#define NONEXC2 (1<<B_TC2XC2S)
#define TIOA0XC2 (2<<B_TC2XC2S)
#define TIOA1XC2 (3<<B_TC2XC2S)
/*---------------------------------------*/
/* Timer Counter Handler type definition */
/*---------------------------------------*/
//typedef void (*TypeTCHandler) ( StructTC *tc_pt ) ;
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
#define NB_TC_BLOCK 1
#define NB_TIMER (NB_TC_BLOCK*NB_TC_CHANNEL)
#define TCB0_BASE ((StructTCBlock *)0xFFFE0000)
//#include "Include/eb01.h"
/* Red Led */
#define LED1 P1
/* Amber Led */
#define LED2 P4
/* Green Led */
#define LED3 P2
/* SW3 Push Button */
#define IRQ_SW3 FIQ
#define PIN_SW3 P12
/* SW4 Push Button */
#define PIN_SW4 P5
/* SW5 Push Button */
#define IRQ_SW5 IRQ0
#define PIN_SW5 P9
/*--------------*/
/* Master Clock */
/*--------------*/
#define MCK 32768000
#define MCKMHz (MCK/1000000)
//#include "Include/aic.h"
/*-------------------------------------------*/
/* Interrupt Controller Structure Definition */
/*-------------------------------------------*/
typedef struct
{
at91_reg AIC_SMR[32] ; /* Source Mode Register */
at91_reg AIC_SVR[32] ; /* Source Vector Register */
at91_reg AIC_IVR ; /* Interrupt Vector Register */
at91_reg AIC_FVR ; /* FIQ Vector Register */
at91_reg AIC_ISR ; /* Interrupt Status Register */
at91_reg AIC_IPR ; /* Interrupt Pending Register */
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