📄 vm51.h
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#ifndef __VM51_HEADER__
#define __VM51_HEADER__
#define __VM51_DEBUG__ 1
#undef __VM51_DEBUG__
#define MAX_PARAM 3
#define BLOCK_SIZE 512
#define MAX_LINE 1024
/*********** my type define *********/
typedef unsigned char U8;
typedef unsigned short U16;
typedef unsigned int U32;
typedef signed char S8;
typedef signed short S16;
typedef signed int S32;
#define TRUE 1
#define FALSE 0
#define ON 1
#define OFF 0
S16 debug;
unsigned long tick; // instructions time,in machine period
unsigned int code_len;
#define ROM_SIZE 64*1024
#define RAM_SIZE 64*1024 // should be 256,set to 64k to avoid memory overflow to debug
U8 ROM[ROM_SIZE];
U8 RAM[RAM_SIZE];
/************** define SFR registers and Program Counter(PC) ****/
U16 PC; //programme counter
#define ACC RAM[0xE0]
#define B RAM[0xF0]
#define PSW RAM[0xD0]
#define SP RAM[0x81]
#define DPL RAM[0x82]
#define DPH RAM[0x83]
#define IE RAM[0xA8]
#define IP RAM[0xD8]
#define P0 RAM[0x80]
#define P1 RAM[0x90]
#define P2 RAM[0xA0]
#define P3 RAM[0xB0]
#define PCON RAM[0x87]
#define SCON RAM[0x98]
#define SBUF RAM[0x99]
#define TCON RAM[0x88]
#define TMOD RAM[0x89]
#define TL0 RAM[0x8A]
#define TL1 RAM[0x8B]
#define TH0 RAM[0x8C]
#define TH1 RAM[0x8D]
/*************** define register set *****************/
#define R0 RAM[0x00]
#define R1 RAM[0x01]
#define R2 RAM[0x02]
#define R3 RAM[0x03]
#define R4 RAM[0x04]
#define R5 RAM[0x05]
#define R6 RAM[0x06]
#define R7 RAM[0x07]
#define R(n) RAM[((PSW&0x18)>>3)*8+(n)] // get Rn's value
/***************************************/
/******define instructions code**************/
/******note: ACALL and AJMP not implement****/
/***************************************/
/****** one byte instructions *************/
#define ADD_A_R(n) (0x28+(n)) // ADD A,Rn(28-2F)
#define ADD_A_aR(i) (0x26+(i)) // ADD A,@Ri(26-27)
#define ADDC_A_R(n) (0x38+(n)) // ADDC A,Rn(38-3F)
#define ADDC_A_aR(i) (0x36+(i)) // ADDC A,@Ri(36-37)
#define ANL_A_R(n) (0x58+(n)) // ANL A,Rn(58-5F)
#define ANL_A_aR(i) (0x56+(i)) // ANL A,@Ri(56-57)
#define CLR_A (0xE4) // CLR A(E4)
#define CLR_C (0xC3) // CLR C(C3)
#define CPL_A (0xF4) // CPL A(F4)
#define CPL_C (0xB3) // CPL C(B3)
#define DA_A (0xD4) // DA A(D4)
#define DEC_A (0x14) // DEC A(14)
#define DEC_R(n) (0x18+(n)) // DEC Rn(18-1F)
#define DEC_aR(i) (0x16+(i)) // DEC @Ri(16-17)
#define DIV_AB (0x84) // DIV AB(84)
#define INC_A (0x04) // INC A(04)
#define INC_R(n) (0x08+(n)) // INC Rn(08-0F)
#define INC_aR(i) (0x06+(i)) // INC @Ri(06-07)
#define INC_DPTR (0xA3) // INC DPTR(A3)
#define JMP_aA_DPTR (0x73) // JMP @A+DPTR(73)
#define MOV_A_R(n) (0xE8+(n)) // MOV A,Rn(E8-EF)
#define MOV_A_aR(i) (0xE6+(i)) // MOV A,@Ri(E6-E7)
#define MOV_R_A(n) (0xF8+(n)) // MOV Rn,A(F8-FF)
#define MOV_aR_A(i) (0xF6+(i)) // MOV @Ri,A(F6-F7)
#define MOVC_A_aA_DPTR (0x93) // MOVC A,@A+DPTR(93)
#define MOVC_A_aA_PC (0x83) // MOVC A,@A+PC(83)
#define MOVX_A_aR(i) (0xE2+(i)) // MOVX A,@Ri(E2-E3)
#define MOVX_A_aDPTR (0xE0) // MOVX A,@DPTR(E0)
#define MOVX_aR_A(i) (0xF2+(i)) // MOVX @Ri,A(F2-F3)
#define MOVX_aDPTR_A (0xF0) // MOVX @DPTR,A(F0)
#define MUL_AB (0xA4) // MUL AB(A4)
#define NOP (0x00) // NOP(00)
#define ORL_A_R(n) (0x48+(n)) // ORL A,Rn(48-4F)
#define ORL_A_aR(i) (0x46+(i)) // ORL A,@Ri(46-47)
#define RET (0x22) // RET(22)
#define RETI (0x32) // RETI(32)
#define RL_A (0x23) // RL A(23)
#define RLC_A (0x33) // RLC A(33)
#define RR_A (0x03) // RR A(03)
#define RRC_A (0x13) // RRC A(13)
#define SETB_C (0xD3) // SETB C(D3)
#define SUBB_A_R(n) (0x98+(n)) // SUBB A,Rn(98-9F)
#define SUBB_A_aR(i) (0x96+(i)) // SUBB A,@Ri(96-97)
#define SWAP_A (0xC4) // SWAP A(C4)
#define XCH_A_R(n) (0xC8+(n)) // XCH A,Rn(C8-CF)
#define XCH_A_aR(i) (0xC6+(i)) // XCH A,@Ri(C6-C7)
#define XCHD_A_aR(i) (0xD6+(i)) // XCHD A,@Ri(D6-D7)
#define XRL_A_R(n) (0x68+(n)) // XRL A,Rn(68-6F)
#define XRL_A_aR(i) (0x66+(i)) // XRL A,@Ri(66-67)
/****** two byte instructions ***************/
/****** distinct by its first byte **********/
#define ADD_A_direct (0x25) // ADD A,direct(25 direct)
#define ADD_A_data (0x24) // ADD A,#data(24 data)
#define ADDC_A_direct (0x35) // ADDC A,direct(35 direct)
#define ADDC_A_data (0x34) // ADDC A,#data(35 data)
#define ANL_A_direct (0x55) // ANL A,direct(55 direct)
#define ANL_A_data (0x54) // ANL A,#data(54 data)
#define ANL_direct_A (0x52) // ANL direct,A(52 direct)
#define ANL_C_bit (0x82) // ANL C,bit(82 bit)
#define ANL_C_bit_ (0xB0) // ANL C,/bit(B0 bit)
#define CLR_bit (0xC2) // CLR bit(C2 bit)
#define CPL_bit (0xB2) // CPL bit(B2 bit)
#define DEC_direct (0x15) // DEC direct(15 direct)
#define DJNZ_R_rel(n) (0xD8+(n)) // DJNZ Rn,rel(D8-DF rel)
#define INC_direct (0x05) // INC direct(05 direct)
#define JC_rel (0x40) // JC rel(40 rel)
#define JNC_rel (0x50) // JNC rel(50 rel)
#define JNZ_rel (0x70) // JNZ rel(70 rel)
#define JZ_rel (0x60) // JZ rel(60 rel)
#define MOV_A_direct (0xE5) // MOV A,direct(E5 direct)
#define MOV_A_data (0x74) // MOV A,#data(74 data)
#define MOV_R_direct(n) (0xA8+(n)) // MOV Rn,direct(A8-AF direct)
#define MOV_R_data(n) (0x78+(n)) // MOV Rn,#data(78-7F data)
#define MOV_direct_A (0xF5) // MOV direct,A(F5 direct)
#define MOV_direct_R(n) (0x88+(n)) // MOV direct,Rn(88-8F direct)
#define MOV_direct_aR(i) (0x86+(i)) // MOV direct,@Ri(86-87 direct)
#define MOV_aR_direct(i) (0xA6+(i)) // MOV @Ri,direct(A6-A7 direct)
#define MOV_aR_data(i) (0x76+(i)) // MOV @Ri,#data(76-77 data)
#define MOV_C_bit (0xA2) // MOV C,bit(A2 bit)
#define MOV_bit_C (0x92) // MOV bit,C(92 bit)
#define ORL_A_direct (0x45) // ORL A,direct(45 direct)
#define ORL_A_data (0x44) // ORL A,#data(44 data)
#define ORL_direct_A (0x42) // ORL direct,A(42 direct)
#define ORL_C_bit (0x72) // ORL C,bit(72 bit)
#define ORL_C_bit_ (0xA0) // ORL C,/bit(A0 bit)
#define POP_direct (0xD0) // POP direct(D0 direct)
#define PUSH_direct (0xC0) // PUSH direct(C0 direct)
#define SETB_bit (0xD2) // SETB bit(D2 bit)
#define SJMP_rel (0x80) // SJMP rel(80 rel)
#define SUBB_A_direct (0x95) // SUBB A,direct(95 direct)
#define SUBB_A_data (0x94) // SUBB A,#data(94 data)
#define XCH_A_direct (0xC5) // XCH A,direct(C5 direct)
#define XRL_A_direct (0x65) // XRL A,direct(65 direct)
#define XRL_A_data (0x64) // XRL A,#data(64 data)
#define XRL_direct_A (0x62) // XRL direct,A(62 direct)
/****** three byte instructions *************/
/****** distinct by its first byte **********/
#define ANL_direct_data (0x53) // ANL direct,#data(53 direct data)
#define CJNE_A_direct_rel (0xB5) // CJNE A,direct,rel(B5 direct rel)
#define CJNE_A_data_rel (0xB4) // CJNE A,#data,rel(B4 data rel)
#define CJNE_R_data_rel(n) (0xB8+(n)) // CJNE Rn,#data,rel(B8-BF data rel)
#define CJNE_aR_data_rel(i) (0xB6+(i)) // CJNE @Ri,#data,rel(B6-B7 data rel)
#define DJNZ_direct_rel (0xD5) // DJNZ direct,rel(D5 direct rel)
#define JB_bit_rel (0x20) // JB bit,rel(20 bit rel)
#define JBC_bit_rel (0x10) // JBC bit,rel(10 bit rel)
#define JNB_bit_rel (0x30) // JNB bit,rel(30 bit rel)
#define LCALL_addr16 (0x12) // LCALL addr16(12 addr15-8 addr7-0)
#define LJMP_addr16 (0x02) // LJMP addr16(02 addr15-8 addr7-0)
#define MOV_direct2_direct1 (0x85) // MOV direct2,direct1(85 direct2 direct1)
#define MOV_direct_data (0x75) // MOV direct,#data(75 direct data)
#define MOV_DPTR_data16 (0x90) // MOV DPTR,#data16(90 data15-8 data7-0)
#define ORL_direct_data (0x43) // ORL direct,#data(43 direct data)
#define XRL_direct_data (0x63) // XRL direct,#data(63 direct data)
/*********** bit operate macros *************/
/*********** SET OR CLR PSW *****************/
/*********PSW***********/
#define SET_CY PSW|=0x80
#define CLR_CY PSW&=~0x80
#define GET_CY PSW&0x80
#define SET_AC PSW|=0x40
#define CLR_AC PSW&=~0x40
#define GET_AC PSW&0x40
#define SET_F0 PSW|=0x20
#define CLR_F0 PSW&=~0x20 // FO IS USER-FLAG
#define GET_F0 PSW&0x20
#define SET_RS1 PSW|=0x10 // RS1-RS0 DETERMINE REGISTER SET
#define CLR_RS1 PSW&=~0x10
#define GET_RS1 PSW&0x10
#define SET_RS0 PSW|=0x08
#define CLR_RS0 PSW&=~0x08
#define GET_RS0 PSW&0x08
#define SET_OV PSW|=0x04
#define CLR_OV PSW&=~0x04
#define GET_OV PSW&0x04
#define SET_P PSW|=0x01
#define CLR_P PSW&=~0x01
#define GET_P PSW&0x01
/**********TCON****************/
#define SET_TF1 TCON|=0x80 // TIMER 1 OVERFLOW INTR FLAG
#define CLR_TF1 TCON&=~0x80
#define GET_TF1 TCON&0x80
#define SET_TR1 TCON|=0x40 // TIMER 1 START or STOP
#define CLR_TR1 TCON&=~0x40
#define GET_TR1 TCON&0x40
#define SET_TF0 TCON|=0x20 // TIMER 0 OVERFLOW INTR FLAG
#define CLR_TF0 TCON&=~0x20
#define GET_TF0 TCON&0x20
#define SET_TR0 TCON|=0x10 // TIMER 0 START or STOP
#define CLR_TR0 TCON&=~0x10
#define GET_TR0 TCON&0x10
#define SET_IE1 TCON|=0x08 // EXTRA INT 1(/INT1) INTR FLAG
#define CLR_IE1 TCON&=~0x08
#define GET_IE1 TCON&0x80
#define SET_IT1 TCON|=0x04 // IT1=0,LEVEL-TRIG;IT1=1,EDGE-TRIG
#define CLR_IT1 TCON&=~0x04
#define GET_IT1 TCON&0x04
#define SET_IE0 TCON|=0x02 // EXTRA INT 0(/INT0) INTR FLAG
#define CLR_IE0 TCON&=~0x02
#define GET_IE0 TCON&0x02
#define SET_IT0 TCON|=0x01 // IT0=0,LEVEL-TRIG;IT0=1,EDGE-TRIG
#define CLR_IT0 TCON&=~0x01
#define GET_IT0 TCON&0x01
/*************SCON************/
#define SET_TI SCON|=0x02 // Series port transmit flag,cleared by software
#define CLR_TI SCON&=~0x02
#define GET_TI SCON&0x02
#define SET_RI SCON|=0x01 // Series port receive flag,cleared by software
#define CLR_RI SCON&=~0x01
#define GET_RI SCON&0x01
/************IE***************/
#define SET_EA IE|=0x80 // ENABLE ALL INTR
#define CLR_EA IE&=~0x80
#define GET_EA IE&0x80
#define SET_ES IE|=0x10 // SERIES PORT INTR ENABLE
#define CLR_ES IE&=~0x10
#define GET_ES IE&0x10
#define SET_ET1 IE|=0x08 // TIMER/COUNTER 1(T1) INTR FLAG
#define CLR_ET1 IE&=~0x08
#define GET_ET1 IE&0x08
#define SET_EX1 IE|=0x04 // EXTRA INTR 1(/INT1) FLAG
#define CLR_EX1 IE&=~0x04
#define GET_EX1 IE&0x04
#define SET_ET0 IE|=0x02 // TIMER/COUNTER 0(T0) INTR FLAG
#define CLR_ET0 IE&=~0x02
#define GET_ET0 IE&0x02
#define SET_EX0 IE|=0x01 // EXTRA INTR 0(/INT0) FLAG
#define CLR_EX0 IE&=~0x01
#define GET_EX0 IE&0x01
/**********IP***************/
#define SET_PS IP|=0x10 // SERIES PORT PRECEDENCE
#define CLR_PS IP&=~0x10
#define GET_PS IP&0x10
#define SET_PT1 IP|=0x08 // TIMER/COUNTER 1(T1) PRECEDENCE
#define CLR_PT1 IP&=~0x08
#define GET_PT1 IP&0x08
#define SET_PX1 IP|=0x04 // EXTRA INTR 1(/INT1) PRECEDENCE
#define CLR_PX1 IP&=~0x04
#define GET_PX1 IP&0x04
#define SET_PT0 IP|=0x02 // TIMER/COUNTER 0(T0) PRECEDENCE
#define CLR_PT0 IP&=~0x02
#define GET_PT0 IP&0x02
#define SET_PX0 IP|=0x01 // EXTRA INTR 0(/INT0) PRECEDENCE
#define CLR_PX0 IP&=~0x01
#define GET_PX0 IP&0x01
/*********** GET or SET or CLR bit access area *****/
/*********** b = 00H-7FH *************************/
#define GET_BIT(b) (RAM[0x20+(b)/8]&((0x01)<<((b)%8)))
#define SET_BIT(b) (RAM[0x20+(b)/8]|((0x01)<<((b)%8)))
#define CLR_BIT(b) (RAM[0x20+(b)/8]& ~((0x01)<<((b)%8)))
/**************************************/
/*******FUNCTION PROTOTYPE**********************/
/**************************************/
int VM51_parse_command(int argc,char *argv[]);
int VM51_output_reg(void);
int VM51_output_mem(void);
int VM51_debug(void);
int VM51_init(void);
int VM51_exec(void);
int VM51_intr(void);
int VM51_test(void);
#endif //end of __VM51_HEADER__
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