📄 vm51_exec.c
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PC = PC + 2 + (S8)(ROM[PC+1]);
break;
}
PC += 2;
break;
}
case INC_direct: // INC direct(05 direct)
RAM[ROM[PC+1]] += 1;
if (debug) // disassembly
printf("Instruction: INC %02XH\n",ROM[PC+1]);
PC += 2;
break;
case JC_rel: // JC rel(40 rel)
if (debug) // disassembly
printf("Instruction: JC %02XH\n",ROM[PC+1]);
if (GET_CY){
PC = PC + 2 + (S8)(ROM[PC+1]);
break;
}
PC += 2;
break;
case JNC_rel: // JNC rel(50 rel)
if (debug) // disassembly
printf("Instruction: JNC %02XH\n",ROM[PC+1]);
if (!GET_CY){
PC = PC + 2 + (S8)(ROM[PC+1]);
break;
}
PC += 2;
break;
case JNZ_rel: // JNZ rel(70 rel)
if (debug) // disassembly
printf("Instruction: JNZ %02XH\n",ROM[PC+1]);
if (ACC){
PC = PC + 2 + (S8)(ROM[PC+1]);
break;
}
PC += 2;
break;
case JZ_rel: // JZ rel(60 rel)
if (debug) // disassembly
printf("Instruction: JZ %02XH\n",ROM[PC+1]);
if (!ACC){
PC = PC + 2 + (S8)(ROM[PC+1]);
break;
}
PC += 2;
break;
case MOV_A_direct: // MOV A,direct(E5 direct)
ACC = RAM[ROM[PC+1]];
if (debug) // disassembly
printf("Instruction: MOV A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
case MOV_A_data: // MOV A,#data(74 data)
ACC = ROM[PC+1];
if (debug) // disassembly
printf("Instruction: MOV A,#%02XH\n",ROM[PC+1]);
PC += 2;
break;
case MOV_R_direct(0): // MOV Rn,direct(A8-AF direct)
case MOV_R_direct(1):
case MOV_R_direct(2):
case MOV_R_direct(3):
case MOV_R_direct(4):
case MOV_R_direct(5):
case MOV_R_direct(6):
case MOV_R_direct(7):
{
n = cmd - 0xA8;
R(n) = RAM[ROM[PC+1]];
if (debug) // disassembly
printf("Instruction: MOV R%d,%02XH\n",n,ROM[PC+1]);
PC += 2;
break;
}
case MOV_R_data(0): // MOV Rn,#data(78-7F data)
case MOV_R_data(1):
case MOV_R_data(2):
case MOV_R_data(3):
case MOV_R_data(4):
case MOV_R_data(5):
case MOV_R_data(6):
case MOV_R_data(7):
{
n = cmd - 0x78;
R(n) = ROM[PC+1];
if (debug) // disassembly
printf("Instruction: MOV R%d,#%02XH\n",n,ROM[PC+1]);
PC += 2;
break;
}
case MOV_direct_A: // MOV direct,A(F5 direct)
{
RAM[ROM[PC+1]] = ACC;
if (debug) // disassembly
printf("Instruction: MOV %02XH,A\n",ROM[PC+1]);
PC += 2;
break;
}
case MOV_direct_R(0): // MOV direct,Rn(88-8F direct)
case MOV_direct_R(1):
case MOV_direct_R(2):
case MOV_direct_R(3):
case MOV_direct_R(4):
case MOV_direct_R(5):
case MOV_direct_R(6):
case MOV_direct_R(7):
{
n = cmd - 0x88;
RAM[ROM[PC+1]] = R(n);
if (debug) // disassembly
printf("Instruction: MOV %02XH,R%d\n",ROM[PC+1],n);
PC += 2;
break;
}
case MOV_direct_aR(0): // MOV direct,@Ri(86-87 direct)
case MOV_direct_aR(1):
{
i = cmd - 0x86;
RAM[ROM[PC+1]] = RAM[R(i)];
if (debug) // disassembly
printf("Instruction: MOV %02XH,@R%d\n",ROM[PC+1],i);
PC += 2;
break;
}
case MOV_aR_direct(0): // MOV @Ri,direct(A6-A7 direct)
case MOV_aR_direct(1):
{
i = cmd - 0xA6;
RAM[R(i)] = RAM[ROM[PC+1]];
if (debug) // disassembly
printf("Instruction: MOV @R%d,%02XH\n",i,ROM[PC+1]);
PC += 2;
break;
}
case MOV_aR_data(0): // MOV @Ri,#data(76-77 data)
case MOV_aR_data(1):
{
i = cmd - 0x76;
RAM[R(i)] = ROM[PC+1];
if (debug) // disassembly
printf("Instruction: MOV @R%d,#%02XH\n",i,ROM[PC+1]);
PC += 2;
break;
}
case MOV_C_bit: // MOV C,bit(A2 bit)
{
if (GET_BIT(ROM[PC+1]))
SET_CY;
else
CLR_CY;
if (debug) // disassembly
printf("Instruction: MOV C,%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case MOV_bit_C: // MOV bit,C(92 bit)
{
if (GET_CY)
SET_BIT(ROM[PC+1]);
else
CLR_BIT(ROM[PC+1]);
if (debug) // disassembly
printf("Instruction: MOV %02XH,C\n",ROM[PC+1]);
PC += 2;
break;
}
case ORL_A_direct: // ORL A,direct(45 direct)
ACC |= RAM[ROM[PC+1]];
if (debug) // disassembly
printf("Instruction: ORL A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
case ORL_A_data: // ORL A,#data(44 data)
ACC |= ROM[PC+1];
if (debug) // disassembly
printf("Instruction: ORL A,#%02XH\n",ROM[PC+1]);
PC += 2;
break;
case ORL_direct_A: // ORL direct,A(42 direct)
RAM[ROM[PC+1]] |= ACC;
if (debug) // disassembly
printf("Instruction: ORL %02XH,A\n",ROM[PC+1]);
PC += 2;
break;
case ORL_C_bit: // ORL C,bit(72 bit)
if (GET_CY || GET_BIT(ROM[PC+1]))
SET_CY;
if (debug) // disassembly
printf("Instruction: ORL C,%02XH\n",ROM[PC+1]);
PC += 2;
break;
case ORL_C_bit_: // ORL C,/bit(A0 bit)
if (GET_CY || ~(GET_BIT(ROM[PC+1])))
SET_CY;
if (debug) // disassembly
printf("Instruction: ORL C,/%02XH\n",ROM[PC+1]);
PC += 2;
break;
case POP_direct: // POP direct(D0 direct)
RAM[ROM[PC+1]] = RAM[SP];
SP -= 1;
if (debug) // disassembly
printf("Instruction: POP %02XH\n",ROM[PC+1]);
PC += 2;
break;
case PUSH_direct: // PUSH direct(C0 direct)
SP += 1;
RAM[SP] = RAM[ROM[PC+1]];
if (debug) // disassembly
printf("Instruction: PUSH %02XH\n",ROM[PC+1]);
PC += 2;
break;
case SETB_bit: // SETB bit(D2 bit)
SET_BIT(ROM[PC+1]);
if (debug) // disassembly
printf("Instruction: SETB %02XH\n",ROM[PC+1]);
PC += 2;
break;
case SJMP_rel: // SJMP rel(80 rel)
if (debug) // disassembly
printf("Instruction: SJMP %02XH\n",ROM[PC+1]);
PC = PC + 2 + (S8)(ROM[PC+1]);
break;
case SUBB_A_direct: // SUBB A,direct(95 direct)
{
U8 borrow;
if (GET_CY)
borrow = 1;
else
borrow = 0;
ACC = (ACC - RAM[ROM[PC+1]] - borrow);
if (debug) // disassembly
printf("Instruction: SUBB A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case SUBB_A_data: // SUBB A,#data(94 data)
{
U8 borrow;
if (GET_CY)
borrow = 1;
else
borrow = 0;
ACC = (ACC - ROM[PC+1] - borrow);
if (debug) // disassembly
printf("Instruction: SUBB A,#%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case XCH_A_direct: // XCH A,direct(C5 direct)
{
U8 tmp;
tmp = ACC;
ACC = RAM[ROM[PC+1]];
RAM[ROM[PC+1]] = tmp;
if (debug) // disassembly
printf("Instruction: XCH A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case XRL_A_direct: // XRL A,direct(65 direct)
ACC ^= RAM[ROM[PC+1]];
if (debug) // disassembly
printf("Instruction: XRL A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
case XRL_A_data: // XRL A,#data(64 data)
ACC ^= ROM[PC+1];
if (debug) // disassembly
printf("Instruction: XRL A,#%02XH\n",ROM[PC+1]);
PC += 2;
break;
case XRL_direct_A: // XRL direct,A(62 direct)
RAM[ROM[PC+1]] ^= ACC;
if (debug) // disassembly
printf("Instruction: XRL %02XH,A\n",ROM[PC+1]);
PC += 2;
break;
/************ THREE TYTES INSTRUCTION **************/
case ANL_direct_data: // ANL direct,#data(53 direct data)
RAM[ROM[PC+1]] &= ROM[PC+2];
if (debug) // disassembly
printf("Instruction: ANL %02XH,#%02XH\n",ROM[PC+1],ROM[PC+2]);
PC += 3;
break;
case CJNE_A_direct_rel: // CJNE A,direct,rel(B5 direct rel)
if (debug) // disassembly
printf("Instruction: CJNE A,%02XH,%02XH\n",ROM[PC+1],ROM[PC+2]);
if (ACC != RAM[ROM[PC+1]]){
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
case CJNE_A_data_rel: // CJNE A,#data,rel(B4 data rel)
if (debug) // disassembly
printf("Instruction: CJNE A,#%02XH,%02XH\n",ROM[PC+1],ROM[PC+2]);
if (ACC != ROM[PC+1]){
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
case CJNE_R_data_rel(0): // CJNE Rn,#data,rel(B8-BF data rel)
case CJNE_R_data_rel(1):
case CJNE_R_data_rel(2):
case CJNE_R_data_rel(3):
case CJNE_R_data_rel(4):
case CJNE_R_data_rel(5):
case CJNE_R_data_rel(6):
case CJNE_R_data_rel(7):
{
if (debug) // disassembly
printf("Instruction: CJNE R%d,#%02XH,%02XH\n",n,ROM[PC+1],ROM[PC+2]);
n = cmd - 0xB8;
if (R(n) != RAM[ROM[PC+1]]){
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
}
case CJNE_aR_data_rel(0): // CJNE @Ri,#data,rel(B6-B7 data rel)
case CJNE_aR_data_rel(1):
{
if (debug) // disassembly
printf("Instruction: CJNE @R%d,#%02XH,%02XH\n",i,ROM[PC+1],ROM[PC+2]);
i = cmd - 0xB6;
if (RAM[R(i)] != ROM[PC+1]){
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
}
case DJNZ_direct_rel: // DJNZ direct,rel(D5 direct rel)
if (debug) // disassembly
printf("Instruction: DJNZ %02XH,%02XH\n",ROM[PC+1],ROM[PC+2]);
RAM[ROM[PC+1]] -= 1;
if (RAM[ROM[PC+1]]){
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
case JB_bit_rel: // JB bit,rel(20 bit rel)
if (debug) // disassembly
printf("Instruction: JB %02XH,%02XH\n",ROM[PC+1],ROM[PC+2]);
if (GET_BIT(ROM[PC+1])){
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
case JBC_bit_rel: // JBC bit,rel(10 bit rel)
if (debug) // disassembly
printf("Instruction: JBC %02XH,%02XH\n",ROM[PC+1],ROM[PC+2]);
if (GET_BIT(ROM[PC+1])){
CLR_BIT(ROM[PC+1]);
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
case JNB_bit_rel: // JNB bit,rel(30 bit rel)
if (debug) // disassembly
printf("Instruction: JNB %02XH,%02XH\n",ROM[PC+1],ROM[PC+2]);
if (!GET_BIT(ROM[PC+1])){
PC = PC + 3 + (S8)(ROM[PC+2]);
break;
}
PC += 3;
break;
case LCALL_addr16: // LCALL addr16(12 addr15-8 addr7-0)
{
U16 temp;
U8 tmp1,tmp2;
tmp1 = ROM[PC+1];
tmp2 = ROM[PC+2];
temp = (U16)(tmp1<<8 + tmp2);
if (debug) // disassembly
printf("Instruction: LCALL %04XH\n",temp);
PC += 3;
SP += 1;
RAM[SP] = tmp2;
SP += 1;
RAM[SP] = tmp1;
PC = temp;
break;
}
case LJMP_addr16: // LJMP addr16(02 addr15-8 addr7-0)
{
U16 temp;
U8 tmp1,tmp2;
tmp1 = ROM[PC+1];
tmp2 = ROM[PC+2];
temp = (U16)(tmp1<<8 + tmp2);
if (debug) // disassembly
printf("Instruction: LJMP %04XH\n",temp);
PC = temp;
break;
}
case MOV_direct2_direct1: // MOV direct2,direct1(85 direct2 direct1)
RAM[ROM[PC+1]] = RAM[ROM[PC+2]];
if (debug) // disassembly
printf("Instruction: MOV %02XH,%02XH\n",ROM[PC+1],ROM[PC+2]);
PC += 3;
break;
case MOV_direct_data: // MOV direct,#data(75 direct data)
RAM[ROM[PC+1]] = ROM[PC+2];
if (debug) // disassembly
printf("Instruction: MOV %02XH,#%02XH\n",ROM[PC+1],ROM[PC+2]);
PC += 3;
break;
case MOV_DPTR_data16: // MOV DPTR,#data16(90 data15-8 data7-0)
DPH = ROM[PC+1];
DPL = ROM[PC+2];
if (debug) // disassembly
printf("Instruction: MOV DPTR,#%04XH\n",(U16)(ROM[PC+1]<<8+ROM[PC+2]));
PC += 3;
break;
case ORL_direct_data: // ORL direct,#data(43 direct data)
RAM[ROM[PC+1]] |= ROM[PC+2];
if (debug) // disassembly
printf("Instruction: ORL %02XH,#%02XH\n",ROM[PC+1],ROM[PC+2]);
PC += 3;
break;
case XRL_direct_data: // XRL direct,#data(63 direct data)
RAM[ROM[PC+1]] ^= ROM[PC+2];
if (debug) // disassembly
printf("Instruction: XRL %02XH,#%02XH\n",ROM[PC+1],ROM[PC+2]);
PC += 3;
break;
/************ UNKNOWN instruction ******************/
default:
fprintf(stderr,"unknown instruction:%02X\n",cmd);
exit(-1);
break;
}
cmd = ROM[PC];
VM51_intr(); // check interrupt or not
}
#ifdef __VM51_DEBUG__
VM51_output_reg();
VM51_output_mem();
#endif
}
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