📄 vm51_exec.c
字号:
break;
}
case MUL_AB: // MUL AB(A4)
{
U16 temp,tmp1,tmp2;
tmp1 = (U16)ACC;
tmp2 = (U16)B;
temp = (U16)(tmp1 * tmp2);
ACC = (temp & 0x00FF);
B = (temp & 0xFF00)>>8;
PC++;
if (debug) // disassembly
printf("Instruction: MUL AB\n");
break;
}
case NOP: // NOP(00)
if (debug) // disassembly
printf("Instruction: NOP\n");
PC++;
break;
case ORL_A_R(0): // ORL A,Rn(48-4F)
case ORL_A_R(1):
case ORL_A_R(2):
case ORL_A_R(3):
case ORL_A_R(4):
case ORL_A_R(5):
case ORL_A_R(6):
case ORL_A_R(7):
{
n = cmd - 0x48;
ACC |= R(n);
if (debug) // disassembly
printf("Instruction: ORL A,R%d\n",n);
PC++;
break;
}
case ORL_A_aR(0): // ORL A,@Ri(46-47)
case ORL_A_aR(1):
{
i = cmd - 0x46;
ACC |= RAM[R(n)];
if (debug) // disassembly
printf("Instruction: ORL A,@R%d\n",i);
PC++;
break;
}
case RET: // RET(22)
{
U8 tmp1,tmp2;
tmp1 = RAM[SP];
SP--;
tmp2 = RAM[SP];
SP--;
PC = (U16)(tmp1<<8 + tmp2);
if (debug) // disassembly
printf("Instruction: RET\n");
// PC++;
break;
}
case RETI: // RETI(32)
{
U8 tmp1,tmp2;
tmp1 = RAM[SP];
SP--;
tmp2 = RAM[SP];
SP--;
PC = (U16)(tmp1<<8 + tmp2);
if (debug) // disassembly
printf("Instruction: RETI\n");
// PC++;
break;
}
case RL_A: // RL A(23)
{
U8 tmp;
tmp = ACC & 0x80;
ACC <<= 1;
if (tmp)
ACC |= 0x01;
if (debug) // disassembly
printf("Instruction: RL A\n");
PC++;
break;
}
case RLC_A: // RLC A(33)
{
U8 tmp1,tmp2;
tmp1 = GET_CY;
tmp2 = ACC & 0x80;
ACC <<= 1;
if (tmp1)
ACC |= 0x01;
if (tmp2)
SET_CY;
else
CLR_CY;
if (debug) // disassembly
printf("Instruction: RLC A\n");
PC++;
break;
}
case RR_A: // RR A(03)
{
U8 tmp;
tmp = ACC & 0x01;
ACC >>= 1;
if (tmp)
ACC |= 0x80;
if (debug) // disassembly
printf("Instruction: RR A\n");
PC++;
break;
}
case RRC_A: // RRC A(13)
{
U8 tmp1,tmp2;
tmp1 = GET_CY;
tmp2 = ACC & 0x01;
ACC >>= 1;
if (tmp1)
ACC |= 0x80;
else
ACC |= ~0x80;
if (tmp2)
SET_CY;
else
CLR_CY;
if (debug) // disassembly
printf("Instruction: RRC A\n");
PC++;
break;
}
case SETB_C: // SETB C(D3)
SET_CY;
if (debug) // disassembly
printf("Instruction: SETB C\n");
PC++;
break;
case SUBB_A_R(0): // SUBB A,Rn(98-9F)
case SUBB_A_R(1):
case SUBB_A_R(2):
case SUBB_A_R(3):
case SUBB_A_R(4):
case SUBB_A_R(5):
case SUBB_A_R(6):
case SUBB_A_R(7):
{
// U8 temp;
U8 borrow;
n = cmd - 0x98;
// temp = ACC;
if (GET_CY)
borrow = 1;
else
borrow = 0;
ACC = (ACC - R(n) - borrow);
if (debug) // disassembly
printf("Instruction: SUBB A,R%d\n",n);
PC++;
break;
}
case SUBB_A_aR(0): // SUBB A,@Ri(96-97)
case SUBB_A_aR(1):
{
U8 borrow;
n = cmd - 0x96;
if(GET_CY)
borrow = 1;
else
borrow = 0;
ACC = (ACC - RAM[R(n)] - borrow);
if (debug) // disassembly
printf("Instruction: SUBB A,@R%d\n",i);
PC++;
break;
}
case SWAP_A: // SWAP A(C4)
{
U8 high,low;
high = (ACC & 0xF0)>>4;
low = (ACC & 0x0F);
ACC = low<<4 + high;
if (debug) // disassembly
printf("Instruction: SWAP A\n");
PC++;
break;
}
case XCH_A_R(0): // XCH A,Rn(C8-CF)
case XCH_A_R(1):
case XCH_A_R(2):
case XCH_A_R(3):
case XCH_A_R(4):
case XCH_A_R(5):
case XCH_A_R(6):
case XCH_A_R(7):
{
U8 tmp;
n = cmd - 0xC8;
tmp = ACC;
ACC = R(n);
R(n) = tmp;
if (debug) // disassembly
printf("Instruction: XCH A,R%d\n",n);
PC++;
break;
}
case XCH_A_aR(0): // XCH A,@Ri(C6-C7)
case XCH_A_aR(1):
{
U8 tmp;
i = cmd - 0xC6;
tmp = ACC;
ACC = RAM[R(i)];
RAM[R(i)] = tmp;
if (debug) // disassembly
printf("Instruction: XCH A,@R%d\n",i);
PC++;
break;
}
case XCHD_A_aR(0): // XCHD A,@Ri(D6-D7)
case XCHD_A_aR(1):
{
U8 tmp1,tmp2;
i = cmd - 0xD6;
tmp1 = ACC & 0x0F;
tmp2 = RAM[R(i)] & 0x0F;
ACC &= 0xF0;
RAM[R(i)] &= 0x0F;
ACC &= tmp2;
RAM[R(i)] &= tmp1;
if (debug) // disassembly
printf("Instruction: XCHD A,@R%d\n",i);
PC++;
break;
}
case XRL_A_R(0): // XRL A,Rn(68-6F)
case XRL_A_R(1):
case XRL_A_R(2):
case XRL_A_R(3):
case XRL_A_R(4):
case XRL_A_R(5):
case XRL_A_R(6):
case XRL_A_R(7):
{
n = cmd - 0x68;
ACC ^= R(n);
if (debug) // disassembly
printf("Instruction: XRL A,R%d\n",n);
PC++;
break;
}
case XRL_A_aR(0): // XRL A,@Ri(66-67)
case XRL_A_aR(1):
{
i = cmd - 0x66;
ACC ^= RAM[R(i)];
if (debug) // disassembly
printf("Instruction: XRL A,@R%d\n",i);
PC++;
break;
}
/************** TWO BYTE INSTUCTION ****************/
case ADD_A_direct: // ADD A,direct(25 direct)
{
U16 temp;
U8 tmp1,tmp2;
temp = (U16)(ACC + RAM[ROM[PC+1]]);
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = RAM[ROM[PC+1]];
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = RAM[ROM[PC+1]];
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADD A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case ADD_A_data: // ADD A,#data(24 data)
{
U16 temp;
U8 tmp1,tmp2;
temp = (U16)(ACC + ROM[PC+1]);
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = ROM[PC+1];
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = ROM[PC+1];
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADD A,#%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case ADDC_A_direct: // ADDC A,direct(35 direct)
{
U16 temp;
U8 tmp1,tmp2;
U8 carry;
if (GET_CY)
carry = 1;
else
carry = 0;
temp = (U16)(ACC + RAM[ROM[PC+1]] + carry);
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = RAM[ROM[PC+1]];
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2+carry>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = RAM[ROM[PC+1]];
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADDC A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case ADDC_A_data: // ADDC A,#data(35 data)
{
U16 temp;
U8 tmp1,tmp2;
U8 carry;
if (GET_CY)
carry = 1;
else
carry = 0;
temp = (U16)(ACC + ROM[PC+1] + carry);
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = ROM[PC+1];
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2+carry>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = ROM[PC+1];
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADDC A,#%02XH\n",ROM[PC+1]);
PC += 2;
break;
}
case ANL_A_direct: // ANL A,direct(55 direct)
ACC &= RAM[ROM[PC+1]];
if (debug) // disassembly
printf("Instruction: ANL A,%02XH\n",ROM[PC+1]);
PC += 2;
break;
case ANL_A_data: // ANL A,#data(54 data)
ACC &= ROM[PC+1];
if (debug) // disassembly
printf("Instruction: ANL A,#%02XH\n",ROM[PC+1]);
PC += 2;
break;
case ANL_direct_A: // ANL direct,A(52 direct)
RAM[ROM[PC+1]] &= ACC;
if (debug) // disassembly
printf("Instruction: ANL %02XH,A\n",ROM[PC+1]);
PC +=2;
break;
case ANL_C_bit: // ANL C,bit(82 bit)
if (GET_CY && GET_BIT(ROM[PC+1]))
SET_CY;
if (debug) // disassembly
printf("Instruction: ANL C,%02XH\n",ROM[PC+1]);
PC += 2;
break;
case ANL_C_bit_: // ANL C,/bit(B0 bit)
if (GET_CY && (~GET_BIT(ROM[PC+1])))
SET_CY;
if (debug) // disassembly
printf("Instruction: ANL A,/%02XH\n",ROM[PC+1]);
PC += 2;
break;
case CLR_bit: // CLR bit(C2 bit)
CLR_BIT(ROM[PC+1]);
if (debug) // disassembly
printf("Instruction: CLR %02XH\n",ROM[PC+1]);
PC += 2;
break;
case CPL_bit: // CPL bit(B2 bit)
if (GET_BIT(ROM[PC+1]))
CLR_BIT(ROM[PC+1]);
else
SET_BIT(ROM[PC+1]);
if (debug) // disassembly
printf("Instruction: CPL %02XH\n",ROM[PC+1]);
PC += 2;
break;
case DEC_direct: // DEC direct(15 direct)
RAM[ROM[PC+1]] -= 1;
if (debug) // disassembly
printf("Instruction: DEC %02XH\n",ROM[PC+1]);
PC += 2;
break;
case DJNZ_R_rel(0): // DJNZ Rn,rel(D8-DF rel)
case DJNZ_R_rel(1):
case DJNZ_R_rel(2):
case DJNZ_R_rel(3):
case DJNZ_R_rel(4):
case DJNZ_R_rel(5):
case DJNZ_R_rel(6):
case DJNZ_R_rel(7):
{
n = cmd - 0xD8;
R(n) -= 1;
if (debug) // disassembly
printf("Instruction: DJNZ R%d,%02XH\n",n,ROM[PC+1]);
if (R(n)){
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