📄 vm51_exec.c
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/*
Name: emu51_exec
Copyright: rockins
Author: rockins
Date: 06-08-05 23:20
Description: this module exec the instructions
*/
#include "vm51.h"
#include <stdio.h>
#include <stdlib.h>
int VM51_exec(void)
{
U8 cmd;
int i;
int n;
// char disasm[MAX_LINE];
if (debug)
printf("===[DEBUG MODE,type H or h for help]===\n");
cmd = ROM[PC];
while (PC <= code_len){
#ifdef __VM51_DEBUG__
printf("Instruction: %02X\n",cmd);
#endif
if (debug)
VM51_debug();
switch(cmd){
/********** ONE BYTE INSTRUCTION ************/
case ADD_A_R(0): // ADD A,Rn(28-2F)
case ADD_A_R(1):
case ADD_A_R(2):
case ADD_A_R(3):
case ADD_A_R(4):
case ADD_A_R(5):
case ADD_A_R(6):
case ADD_A_R(7):
{
U16 temp;
U8 tmp1,tmp2;
n = cmd - 0x28;
temp = (U16)(ACC + R(n));
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = R(n);
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = R(n);
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADD A,R%d\n",n);
PC++;
break;
}
case ADD_A_aR(0): // ADD A,@Ri(26-27)
case ADD_A_aR(1):
{
U16 temp;
U8 tmp1,tmp2;
i = cmd - 0x26;
temp = (U16)(ACC + RAM[R(i)]);
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = RAM[R(i)];
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = RAM[R(i)];
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADD A,@R%d\n",i);
PC++;
break;
}
case ADDC_A_R(0): // ADDC A,Rn(38-3F)
case ADDC_A_R(1):
case ADDC_A_R(2):
case ADDC_A_R(3):
case ADDC_A_R(4):
case ADDC_A_R(5):
case ADDC_A_R(6):
case ADDC_A_R(7):
{
U16 temp;
U8 tmp1,tmp2;
U8 carry;
if (GET_CY)
carry = 1;
else
carry = 0;
n = cmd - 0x38;
temp = (U16)(ACC + R(n) + carry);
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = R(n);
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2+carry>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = R(n);
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADDC A,R%d\n",n);
PC++;
break;
}
case ADDC_A_aR(0): // ADDC A,@Ri(36-37)
case ADDC_A_aR(1):
{
U16 temp;
U8 tmp1,tmp2;
U8 carry;
if (GET_CY)
carry = 1;
else
carry = 0;
i = cmd - 0x36;
temp = (U16)(ACC + RAM[R(i)] +carry);
if (temp > 0xFF) //overflow
SET_OV;
tmp1 = ACC;
tmp2 = RAM[R(i)];
tmp1 &= 0x0F;
tmp2 &= 0x0F;
if (tmp1+tmp2+carry>0x0F) // auxilliary carry
SET_AC;
tmp1 = ACC;
tmp2 = RAM[R(i)];
tmp1 = (tmp1&0xF0)>>4;
tmp2 = (tmp2&0xF0)>>4;
if (tmp1+tmp2>0x0F) // carry
SET_CY;
ACC = (U8)temp;
if (debug) // disassembly
printf("Instruction: ADDC A,@R%d\n",i);
PC++;
break;
}
case ANL_A_R(0): // ANL A,Rn(58-5F)
case ANL_A_R(1):
case ANL_A_R(2):
case ANL_A_R(3):
case ANL_A_R(4):
case ANL_A_R(5):
case ANL_A_R(6):
case ANL_A_R(7):
{
n = cmd - 0x58;
ACC &= R(n);
if (debug) // disassembly
printf("Instruction: ANL A,R%d\n",n);
PC++;
break;
}
case ANL_A_aR(0): // ANL A,@Ri(56-57)
case ANL_A_aR(1):
{
i = cmd - 0x56;
ACC &= RAM[R(i)];
if (debug) // disassembly
printf("Instruction: ANL A,@R%d\n",i);
PC++;
break;
}
case CLR_A: // CLR A(E4)
ACC = 0;
if (debug) // disassembly
printf("Instruction: CLR A\n");
PC++;
break;
case CLR_C: // CLR C(C3)
CLR_CY;
if (debug) // disassembly
printf("Instruction: CLR C\n");
PC++;
break;
case CPL_A: // CPL A(F4)
ACC = ~ACC;
if (debug) // disassembly
printf("Instruction: CPL A\n");
PC++;
break;
case CPL_C: // CPL C(B3)
if (GET_CY)
CLR_CY;
else
SET_CY;
if (debug) // disassembly
printf("Instruction: CPL C\n");
PC++;
break;
case DA_A: // DA A(D4)
{
U8 tmp;
tmp = ACC & 0x0F;
if (tmp > 9 || GET_AC)
ACC += 0x06;
tmp = (ACC & 0xF0)>>4;
if (tmp > 9 || GET_CY)
ACC += 0x60;
if (tmp + 0x06 > 0x0F)
SET_CY;
if (debug) // disassembly
printf("Instruction: DA A\n");
PC++;
break;
}
case DEC_A: // DEC A(14)
ACC -= 1;
if (debug) // disassembly
printf("Instruction: DEC A\n");
PC++;
break;
case DEC_R(0): // DEC Rn(18-1F)
case DEC_R(1):
case DEC_R(2):
case DEC_R(3):
case DEC_R(4):
case DEC_R(5):
case DEC_R(6):
case DEC_R(7):
{
n = cmd - 0x18;
R(n) -= 1;
if (debug) // disassembly
printf("Instruction: DEC R%d\n",n);
PC++;
break;
}
case DEC_aR(0): // DEC @Ri(16-17)
case DEC_aR(1):
{
i = cmd - 0x16;
RAM[R(n)] -= 1;
if (debug) // disassembly
printf("Instruction: DEC @R%d\n",i);
PC++;
break;
}
case DIV_AB: // DIV AB(84)
{
U8 tmp1,tmp2;
// tmp1 = ACC;
// tmp2 = B;
if (debug) // disassembly
printf("Instruction: DIV AB\n");
SET_CY; // Cy always be 0
if (B == 0) // when B==0,overflow
{
SET_OV;
fprintf(stderr,"Panic: Instruction: DIV AB(divided by zero)\n");
PC++;
break;
}
tmp1 = ACC/B;
tmp2 = ACC%B;
ACC = tmp1;
B = tmp2;
PC++;
break;
}
case INC_A: // INC A(04)
ACC += 1;
if (debug) // disassembly
printf("Instruction: INC A\n");
PC++;
break;
case INC_R(0): // INC Rn(08-0F)
case INC_R(1):
case INC_R(2):
case INC_R(3):
case INC_R(4):
case INC_R(5):
case INC_R(6):
case INC_R(7):
{
n = cmd - 0x08;
R(n) += 1;
if (debug) // disassembly
printf("Instruction: INC R%d\n",n);
PC++;
break;
}
case INC_aR(0): // INC @Ri(06-07)
case INC_aR(1):
{
i = cmd - 0x06;
RAM[R(n)] += 1;
if (debug) // disassembly
printf("Instruction: INC @R%d\n",i);
PC++;
break;
}
case INC_DPTR: // INC DPTR(A3)
{
U16 temp;
temp = (U16)(DPH<<8+DPL);
temp += 1;
DPL = (temp & 0x00FF);
DPH = (temp & 0xFF00)>>8;
if (debug) // disassembly
printf("Instruction: INC DPTR\n");
PC++;
break;
}
case JMP_aA_DPTR: // JMP @A+DPTR(73)
{
U16 temp;
temp = (U16)(DPH<<8+DPL);
PC = (U16)(temp + ACC);
if (debug) // disassembly
printf("Instruction: JMP @A+DPTR\n");
// PC++;
break;
}
case MOV_A_R(0): // MOV A,Rn(E8-EF)
case MOV_A_R(1):
case MOV_A_R(2):
case MOV_A_R(3):
case MOV_A_R(4):
case MOV_A_R(5):
case MOV_A_R(6):
case MOV_A_R(7):
{
n = cmd - 0xE8;
ACC = R(n);
if (debug) // disassembly
printf("Instruction: MOV A,R%d\n",n);
PC++;
break;
}
case MOV_A_aR(0): // MOV A,@Ri(E6-E7)
case MOV_A_aR(1):
{
i = cmd - 0xE6;
ACC = RAM[R(n)];
if (debug) // disassembly
printf("Instruction: MOV A,@R%d\n",i);
PC++;
break;
}
case MOV_R_A(0): // MOV Rn,A(F8-FF)
case MOV_R_A(1):
case MOV_R_A(2):
case MOV_R_A(3):
case MOV_R_A(4):
case MOV_R_A(5):
case MOV_R_A(6):
case MOV_R_A(7):
{
n = cmd - 0xF8;
R(n) = ACC;
if (debug) // disassembly
printf("Instruction: MOV R%d,A\n",n);
PC++;
break;
}
case MOV_aR_A(0): // MOV @Ri,A(F6-F7)
case MOV_aR_A(1):
{
i = cmd - 0xF6;
RAM[R(n)] = ACC;
if (debug) // disassembly
printf("Instruction: MOV @R%d,A\n",i);
PC++;
break;
}
case MOVC_A_aA_DPTR: // MOVC A,@A+DPTR(93)
{
U16 temp;
temp = (U16)(DPH<<8+DPL);
ACC = ROM[(U16)(ACC + temp)];
if (debug) // disassembly
printf("Instruction: MOVC A,@A+DPTR\n");
PC++;
break;
}
case MOVC_A_aA_PC: // MOVC A,@A+PC(83)
ACC = ROM[(U16)(ACC + PC)];
if (debug) // disassembly
printf("Instruction: MOVC A,@A+PC\n");
PC++;
break;
case MOVX_A_aR(0): // MOVX A,@Ri(E2-E3)
case MOVX_A_aR(1):
{
i = cmd - 0xE2;
ACC = RAM[R(i)];
if (debug) // disassembly
printf("Instruction: MOVX A,@R%d\n",i);
PC++;
break;
}
case MOVX_A_aDPTR: // MOVX A,@DPTR(E0)
{
U16 temp;
temp = (U16)(DPH<<8+DPL);
ACC = RAM[temp];
if (debug) // disassembly
printf("Instruction: MOVX A,@DPTR\n");
PC++;
break;
}
case MOVX_aR_A(0): // MOVX @Ri,A(F2-F3)
case MOVX_aR_A(1):
{
i = cmd - 0xF2;
RAM[R(i)] = ACC;
if (debug) // disassembly
printf("Instruction: MOVX @R%d,A\n",n);
PC++;
break;
}
case MOVX_aDPTR_A: // MOVX @DPTR,A(F0)
{
U16 temp;
temp = (U16)(DPH<<8+DPL);
RAM[temp] = ACC;
if (debug) // disassembly
printf("Instruction: MOVX @DPTR,A\n");
PC++;
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