cycles.c

ARM 的实例程序

/* everycycle.c - function TraceX called every cycle
 */

#include "minperip.h"
#include "armul_mem.h"
#include "armul_callbackid.h"

#if !defined(NDEBUG)
# if 1
# else
#  define VERBOSE
# endif
#endif

BEGIN_STATE_DECL(cycles)
	ARMul_MemInterface child, *mem_ref, bus_mem;
END_STATE_DECL(cycles)

static int TraceBusMemAccess(void *handle,
                              ARMword address,
                              ARMword *data,
                              ARMul_acc access_type);
                              
static int TraceX(cyclesState *ts, ARMword addr, uint32 *data, int rv,
                   unsigned acc);
                   
static unsigned TraceMemInfo(void *handle, unsigned type, ARMword *pID,
                             uint64 *data);
static ARMTime TraceReadClock(void *handle);
static const ARMul_Cycles *TraceReadCycles(void *handle);
static uint32 TraceGetCycleLength(void *handle);
static int RDI_info(void *handle,unsigned type,ARMword *arg1,ARMword *arg2);


BEGIN_INIT(cycles)
Hostif_PrettyPrint(state->hostif, config, ", everycycle");
{
	/* Now register the access function */
	ARMul_MemInterface *mif;
    uint32 ID[2];
    ID[0] = ARMulBusID_Core;
    ID[1] = 0;
    mif = ARMulif_QueryMemInterface(&state->coredesc, &ID[0]);
    
    assert( mif );
    
    if( mif ) {
    	  state->bus_mem.handle = state;
          state->bus_mem.x.basic.access = TraceBusMemAccess;
      
          state->bus_mem.mem_info=TraceMemInfo;
          state->bus_mem.read_clock=TraceReadClock;
          state->bus_mem.read_cycles=TraceReadCycles;
          state->bus_mem.get_cycle_length = TraceGetCycleLength;

          /* </> */

          switch(mif->memtype) 
          {
          case ARMul_MemType_Basic:
          case ARMul_MemType_16Bit:
          case ARMul_MemType_Thumb:
          case ARMul_MemType_BasicCached:
          case ARMul_MemType_16BitCached:
          case ARMul_MemType_ThumbCached:
          case ARMul_MemType_ARMissAHB:
              break;

          case ARMul_MemType_StrongARM:
              /* (state->bus_mem.x.strongarm.core_exception = TraceCoreException;
              state->bus_mem.x.strongarm.data_cache_busy = TraceDataCacheBusy; */
              
              state->bus_mem.x.strongarm.core_exception = NULL;
              state->bus_mem.x.strongarm.data_cache_busy = NULL;
              break;
          case ARMul_MemType_ARM8:
/*              state->bus_mem.x.arm8.core_exception = TraceCoreException;
              state->bus_mem.x.arm8.access2 = TraceBusMemAccess2;
*/              
              state->bus_mem.x.arm8.core_exception = NULL;
              state->bus_mem.x.arm8.access2 = NULL;
              break;

          case ARMul_MemType_ARMissCache:
          case ARMul_MemType_ARM9:
          case ARMul_MemType_ByteLanes:       
          default:
              break;
          }
      }
      
      ARMulif_InstallUnkRDIInfoHandler(&state->coredesc,
                                   RDI_info,state);
 
      ARMul_InsertMemInterface(mif,
                               &state->child,
                               &state->mem_ref,
                               &state->bus_mem);
}
END_INIT(cycles)


BEGIN_EXIT(cycles)
END_EXIT(cycles)

static int TraceBusMemAccess(void *handle,
                              ARMword address,
                              ARMword *data,
                              ARMul_acc access_type)
{
    cyclesState *ts = (cyclesState *)handle;
    int err = 
        ts->child.x.basic.access(ts->child.handle,address,data,access_type);

    TraceX(ts, address, data, err, access_type);
    return err;
}

static int TraceX(cyclesState *ts, ARMword addr, uint32 *data, int rv,
                   unsigned acc)
{
/* DEBUG catch ALL accesses
  if ((addr<ts->range_lo || (addr>=ts->range_hi && ts->range_hi!=0)))
  {
  }
*/  

	/* display diagnostic message */

	static ARMTime prevtime = 0;
	static ARMTime currtime = 0;

	currtime = ARMulif_Time(&ts->coredesc);

	if( currtime != prevtime ) {
		prevtime = currtime;
		Hostif_ConsolePrint(ts->hostif,"Cycle: %u ", currtime );
		Hostif_ConsolePrint(ts->hostif,"Access address: %u\n", addr );
	}

  return rv;
}


/* -------------------------------------------------------------------- */

static int RDI_info(void *handle,unsigned type,ARMword *arg1,ARMword *arg2)
{
	return RDIError_UnimplementedMessage;
}

static unsigned TraceMemInfo(void *handle, unsigned type, ARMword *pID,
                             uint64 *data)
{
    cyclesState *mem = (cyclesState *)handle;
    if (mem->child.mem_info)
    {
        return mem->child.mem_info(mem->child.handle,type,pID,data);
    }
    else
    {
        return RDIError_UnimplementedMessage;
    }
}

/* Aims to return a value in microseconds */
static ARMTime TraceReadClock(void *handle)
{
    cyclesState *mem = (cyclesState *)handle;
    if (mem->child.read_clock)
    {
        return mem->child.read_clock(mem->child.handle);
    }
    else
    {
        return 0L;
    }    
}

static const ARMul_Cycles *TraceReadCycles(void *handle)
{
    cyclesState *mem = (cyclesState *)handle;
    if (mem->child.read_cycles)
    {
        return mem->child.read_cycles(mem->child.handle);
    }
    else
    {
        return NULL;
    }
}


static uint32 TraceGetCycleLength(void *handle)
{
    cyclesState *mem = (cyclesState *)handle;
    if (mem->child.get_cycle_length)
        return mem->child.get_cycle_length(mem->child.handle);
    /* Todo: Otherwise guess from CCFG and CPUSPEED */
    return 0;
}

/*--- <SORDI STUFF> ---*/

#define SORDI_DLL_NAME_STRING "cycles"
#define SORDI_DLL_DESCRIPTION_STRING "cycles (test only)"
#define SORDI_RDI_PROCVEC cycles_AgentRDI
#include "perip_sordi.h"

#include "perip_rdi_agent.h"
    IMPLEMENT_AGENT_PROCS_NOEXE_NOMODULE(cycles)
    IMPLEMENT_AGENT_PROCVEC_NOEXE(cycles)

/*--- </> ---*/

/* EOF cycles.c */