📄 fet410_ta_pwm01.c
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//*******************************************************************************
// MSP-FET430P410 Demo - Timer_A PWM TA1-2 upmode, DCO SMCLK
//
// Description; This program will generate a two PWM outputs on P1.2/2.0 using
// Timer_A in an upmode. The value in CCR0, 512, defines the period and the
// values in CCR1 and CCR1 the duty PWM cycles. Using 1.048MHz SMCLK as TACLK,
// the timer period is 488us with a 75% duty cycle on P1.2 and 25% on P2.0.
// ACLK = LFXT1 = 32768, MCLK = SMCLK = TACLK = DCO = 32xACLK = 1.048576Mhz
// //*External watch crystal on XIN XOUT is required for ACLK*//
//
// MSP430F413
// -----------------
// /|\| XIN|-
// | | | 32kHz
// --|RST XOUT|-
// | |
// | P1.2|--> CCR1 - 75% PWM
// | P2.0|--> CCR2 - 25% PWM
//
// M.Buccini
// Texas Instruments, Inc
// January 2002
// Built with IAR Embedded Workbench Version: 1.25A
//******************************************************************************
#include <msp430x41x.h>
void main(void)
{
WDTCTL = WDTPW +WDTHOLD; // Stop WDT
TACTL = TASSEL1 + TACLR; // SMCLK, Clear Tar
CCR0 = 512-1; // PWM Period
CCTL1 = OUTMOD_7; // CCR1 reset/set
CCR1 = 384; // CCR1 PWM duty cycle
CCTL2 = OUTMOD_7; // CCR2 reset/set
CCR2 = 128; // CCR2 PWM duty cycle
P1DIR |= 0x04; // P1.2 output
P1SEL |= 0x04; // P1.2 TA1 otion
P2DIR |= 0x01; // P2.0 output
P2SEL |= 0x01; // P2.0 TA2 otion
TACTL |= MC0; // Start Timer_A in up mode
for (;;)
{
_BIS_SR(CPUOFF); // Enter LPM0
_NOP(); // Required only for C-spy
}
}
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