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📄 no4a.lst

📁 AVR-AT90S8535,HD8279,等开发的洁净空调专用DDC系统,包括AD/DA,PID计算等.
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AVRASM ver. 1.54  C:\My Documents\HFAVR1\No4a.asm Thu Oct 31 11:47:33 2002


warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
warning : Register already defined by the .DEF directive
          .include "8535def.inc"
         ;***************************************************************************
         ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
         ;* 
         ;* Number		:AVR000
         ;* File Name		:"8535def.inc"
         ;* Title		:Register/Bit Definitions for the AT90S8535
         ;* Date                 :99.01.28
         ;* Version              :1.30
         ;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
         ;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
         ;* Support E-mail	:avr@atmel.com
         ;* Target MCU		:AT90S8535
         ;*
         ;* DESCRIPTION
         ;* When including this file in the assembly program file, all I/O register	
         ;* names and I/O register bit names appearing in the data book can be used.
         ;* In addition, the six registers forming the three data pointers X, Y and
         ;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
         ;* SRAM is also defined 
         ;*
         ;* The Register names are represented by their hexadecimal address.
         ;* 
         ;* The Register Bit names are represented by their bit number (0-7).
         ;* 
         ;* Please observe the difference in using the bit names with instructions
         ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
         ;* (skip if bit in register set/cleared). The following example illustrates
         ;* this:
         ;* 
         ;* in	r16,PORTB		;read PORTB latch
         ;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
         ;* out  PORTB,r16		;output to PORTB
         ;*
         ;* in	r16,TIFR		;read the Timer Interrupt Flag Register
         ;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
         ;* rjmp	TOV0_is_set		;jump if set
         ;* ...				;otherwise do something else
         ;***************************************************************************
         
         ;***** Specify Device
          .device AT90S8535
         
         ;***** I/O Register Definitions
          .equ	SREG	=$3f
          .equ	SPH	=$3e
          .equ	SPL	=$3d
          .equ	GIMSK	=$3b
          .equ	GIFR	=$3a
          .equ	TIMSK	=$39
          .equ	TIFR	=$38
         
          .equ	MCUCR	=$35
          .equ	MCUSR	=$34
         
          .equ	TCCR0	=$33
          .equ	TCNT0	=$32
         
          .equ	TCCR1A	=$2f
          .equ	TCCR1B	=$2e
          .equ	TCNT1H	=$2d
          .equ	TCNT1L	=$2c
          .equ	OCR1AH	=$2b
          .equ	OCR1AL	=$2a
          .equ	OCR1BH	=$29
          .equ	OCR1BL	=$28
          .equ	ICR1H	=$27
          .equ	ICR1L	=$26
         
          .equ	TCCR2	=$25
          .equ	TCNT2	=$24
          .equ	OCR2	=$23
          .equ	ASSR	=$22
         
          .equ	WDTCR	=$21
          .equ	EEARH	=$1f
          .equ	EEARL	=$1e
          .equ	EEDR	=$1d
          .equ	EECR	=$1c
          .equ	PORTA	=$1b
          .equ	DDRA	=$1a
          .equ	PINA	=$19
          .equ	PORTB	=$18
          .equ	DDRB	=$17
          .equ	PINB	=$16
          .equ	PORTC	=$15
          .equ	DDRC	=$14
          .equ	PINC	=$13
          .equ	PORTD	=$12
          .equ	DDRD	=$11
          .equ	PIND	=$10
          .equ	SPDR	=$0f
          .equ	SPSR	=$0e
          .equ	SPCR	=$0d
          .equ	UDR	=$0c
          .equ	USR	=$0b
          .equ	UCR	=$0a
          .equ	UBRR	=$09
          .equ	ACSR	=$08
          .equ    ADMUX   =$07
          .equ    ADCSR   =$06
          .equ    ADCH    =$05
          .equ    ADCL    =$04
         
         
         ;***** Bit Definitions
         
          .equ	EXTRF	=1
          .equ	PORF	=0
         
          .equ	INT1	=7
          .equ	INT0	=6
         
          .equ	INTF1	=7
          .equ	INTF0	=6
         
          .equ	OCIE2	=7
          .equ	TOIE2	=6
          .equ	TICIE1	=5
          .equ	OCIE1A	=4
          .equ	OCIE1B	=3
          .equ	TOIE1	=2
          .equ	TOIE0	=0
         
          .equ	OCF2	=7
          .equ	TOV2	=6
          .equ	ICF1	=5
          .equ	OCF1A	=4
          .equ	OCF1B	=3
          .equ	TOV1	=2
          .equ	TOV0	=0
         
          .equ	SE	=6
          .equ	SM1	=5
          .equ	SM0	=4
          .equ	ISC11	=3
          .equ	ISC10	=2
          .equ	ISC01	=1
          .equ	ISC00	=0
         
          .equ	CS02	=2
          .equ	CS01	=1
          .equ	CS00	=0
         
          .equ	COM1A1	=7
          .equ	COM1A0	=6
          .equ	COM1B1	=5
          .equ	COM1B0	=4
          .equ	PWM11	=1
          .equ	PWM10	=0
         
          .equ	ICNC1	=7
          .equ	ICES1	=6
          .equ	CTC1	=3
          .equ	CS12	=2
          .equ	CS11	=1
          .equ	CS10	=0
         
          .equ	PWM2	=6
          .equ	COM21	=5
          .equ	COM20	=4
          .equ	CTC2	=3
          .equ	CS22	=2
          .equ	CS21	=1
          .equ	CS20	=0
         
          .equ	AS2	=3
          .equ	TCN2UB	=2
          .equ	OCR2UB	=1
          .equ	TCR2UB	=0
         
          .equ	WDDE	=4
          .equ	WDE	=3
          .equ	WDP2	=2
          .equ	WDP1	=1
          .equ	WDP0	=0
         
          .equ	EERIE	=3
          .equ	EEMWE	=2
          .equ	EEWE	=1
          .equ	EERE	=0
         
          .equ	PA7	=7
          .equ	PA6	=6
          .equ	PA5	=5
          .equ	PA4	=4
          .equ	PA3	=3
          .equ	PA2	=2
          .equ	PA1	=1
          .equ	PA0	=0
         
          .equ	DDA7	=7
          .equ	DDA6	=6
          .equ	DDA5	=5
          .equ	DDA4	=4
          .equ	DDA3	=3
          .equ	DDA2	=2
          .equ	DDA1	=1
          .equ	DDA0	=0
         
          .equ	PINA7	=7
          .equ	PINA6	=6
          .equ	PINA5	=5
          .equ	PINA4	=4
          .equ	PINA3	=3
          .equ	PINA2	=2
          .equ	PINA1	=1
          .equ	PINA0	=0
         
          .equ	PB7	=7
          .equ	PB6	=6
          .equ	PB5	=5
          .equ	PB4	=4
          .equ	PB3	=3
          .equ	PB2	=2
          .equ	PB1	=1
          .equ	PB0	=0
         
          .equ	DDB7	=7
          .equ	DDB6	=6
          .equ	DDB5	=5
          .equ	DDB4	=4
          .equ	DDB3	=3
          .equ	DDB2	=2
          .equ	DDB1	=1
          .equ	DDB0	=0
         
          .equ	PINB7	=7
          .equ	PINB6	=6
          .equ	PINB5	=5
          .equ	PINB4	=4
          .equ	PINB3	=3
          .equ	PINB2	=2
          .equ	PINB1	=1
          .equ	PINB0	=0
         
          .equ	PC7	=7
          .equ	PC6	=6
          .equ	PC5	=5
          .equ	PC4	=4
          .equ	PC3	=3
          .equ	PC2	=2
          .equ	PC1	=1
          .equ	PC0	=0
         
          .equ	DDC7	=7
          .equ	DDC6	=6
          .equ	DDC5	=5
          .equ	DDC4	=4
          .equ	DDC3	=3
          .equ	DDC2	=2
          .equ	DDC1	=1
          .equ	DDC0	=0
         
          .equ	PINC7	=7
          .equ	PINC6	=6
          .equ	PINC5	=5
          .equ	PINC4	=4
          .equ	PINC3	=3
          .equ	PINC2	=2
          .equ	PINC1	=1
          .equ	PINC0	=0
         
          .equ	PD7	=7
          .equ	PD6	=6
          .equ	PD5	=5
          .equ	PD4	=4
          .equ	PD3	=3
          .equ	PD2	=2
          .equ	PD1	=1
          .equ	PD0	=0
         
          .equ	DDD7	=7
          .equ	DDD6	=6
          .equ	DDD5	=5
          .equ	DDD4	=4
          .equ	DDD3	=3
          .equ	DDD2	=2
          .equ	DDD1	=1
          .equ	DDD0	=0
         
          .equ	PIND7	=7
          .equ	PIND6	=6
          .equ	PIND5	=5
          .equ	PIND4	=4
          .equ	PIND3	=3
          .equ	PIND2	=2
          .equ	PIND1	=1
          .equ	PIND0	=0
         
          .equ	SPIE	=7
          .equ	SPE	=6
          .equ	DORD	=5
          .equ	MSTR	=4
          .equ	CPOL	=3
          .equ	CPHA	=2
          .equ	SPR1	=1
          .equ	SPR0	=0
         
          .equ	SPIF	=7
          .equ	WCOL	=6
         
          .equ	RXC	=7
          .equ	TXC	=6
          .equ	UDRE	=5
          .equ	FE	=4
          .equ	OR	=3
         
          .equ	RXCIE	=7
          .equ	TXCIE	=6
          .equ	UDRIE	=5
          .equ	RXEN	=4
          .equ	TXEN	=3
          .equ	CHR9	=2
          .equ	RXB8	=1
          .equ	TXB8	=0
         
          .equ	ACD	=7
          .equ	ACO	=5
          .equ	ACI	=4
          .equ	ACIE	=3
          .equ	ACIC	=2
          .equ	ACIS1	=1
          .equ	ACIS0	=0
         
          .equ	MUX2	=2
          .equ	MUX1	=1
          .equ	MUX0	=0
         
          .equ	ADEN	=7
          .equ	ADSC	=6
          .equ	ADFR	=5
          .equ	ADIF	=4
          .equ	ADIE	=3
          .equ	ADPS2	=2
          .equ	ADPS1	=1
          .equ	ADPS0	=0
         
          .def	XL	=r26
          .def	XH	=r27
          .def	YL	=r28
          .def	YH	=r29
          .def	ZL	=r30
          .def	ZH	=r31
         
          .equ 	RAMEND  =$25F	;Last On-Chip SRAM location
          .equ	XRAMEND =$25F
          .equ	E2END	=$1FF
          .equ	FLASHEND=$FFF
         
          .equ	INT0addr=$001	;External Interrupt0 Vector Address
          .equ	INT1addr=$002	;External Interrupt1 Vector Address
          .equ	OC2addr =$003	;Timer2 compare match Vector Address
          .equ	OVF2addr=$004	;Timer2 overflow Vector Address
          .equ	ICP1addr=$005	;Timer1 Input Capture Vector Address
          .equ	OC1Aaddr=$006	;Timer1 Output Compare A Interrupt Vector Address
          .equ	OC1Baddr=$007	;Timer1 Output Compare B Interrupt Vector Address
          .equ	OVF1addr=$008	;Overflow1 Interrupt Vector Address
          .equ	OVF0addr=$009	;Overflow0 Interrupt Vector Address
          .equ	SPIaddr =$00A	;SPI Interrupt Vector Address
          .equ	URXCaddr=$00B	;UART Receive Complete Interrupt Vector Address
          .equ	UDREaddr=$00C	;UART Data Register Empty Interrupt Vector Address
          .equ	UTXCaddr=$00D	;UART Transmit Complete Interrupt Vector Address
          .equ	ADCCaddr=$00E	;ADC Conversion Complete Interrupt Vector Address
          .equ	ERDYaddr=$00F	;EEPROM Write Complete Interrupt Vector Address
          .equ	ACIaddr =$010	;Analog Comparator Interrupt Vector Address          .org	0x00
         
          .def	mc16uL	=r9		;被乘数低字节
          .def	mc16uH	=r10		;被乘数高字节
          .def	mp16uL	=r11		;乘数低字节
          .def	mp16uH	=r12		;乘数高字节
          .def	m16ua	=r11		;结果 字节 0 (LSB)
          .def	m16ub	=r12		;结果 字节 1
          .def	m16u2	=r13		;结果 字节 2
          .def	m16u3	=r14		;结果 字节 3 (MSB)
          .def	mcnt16u	=r21		;循环计数
000000 c01f      	rjmp	RESET		;reset handle
          .org	0x020
         
          reset:
000020 24aa      	clr	mc16uh
000021 24cc      	clr	mp16uh
         	;ldi	mcnt16u,1
000022 2e95      	mov	mc16ul,mcnt16u
000023 e352      	ldi	mcnt16u,50
000024 2eb5      	mov	mp16ul,mcnt16u
000025 d026      	rcall	mpy16u
         	
000026 2cbb      	mov	mp16ul,m16ua
000027 2ccc      	mov	mp16uh,m16ub
000028 e05b      	ldi	mcnt16u,11
000029 2e95      	mov	mc16ul,mcnt16u
00002a 24aa      	clr	mc16uh
00002b d02f      	rcall	div16u
         	
00002c 2c9b      	mov	mc16ul,m16ua
00002d 2cac      	mov	mc16uh,m16ub
00002e e05a      	ldi	mcnt16u,10
00002f 2eb5      	mov	mp16ul,mcnt16u
000030 24cc      	clr	mp16uh
000031 d01a      	rcall	mpy16u
         	
000032 2cbb      	mov	mp16ul,m16ua
000033 2ccc      	mov	mp16uh,m16ub
000034 e053      	ldi	mcnt16u,3
000035 2e95      	mov	mc16ul,mcnt16u
000036 24aa      	clr	mc16uh
000037 d023      	rcall	div16u
         	
000038 2c9b      	mov	mc16ul,m16ua
000039 2cac      	mov	mc16uh,m16ub
00003a e054      	ldi	mcnt16u,4
00003b 2eb5      	mov	mp16ul,mcnt16u
00003c 24cc      	clr	mp16uh
00003d d00e      	rcall	mpy16u
         	
00003e 2cbb      	mov	mp16ul,m16ua
00003f 2ccc      	mov	mp16uh,m16ub
000040 e15f      	ldi	mcnt16u,31
000041 2e95      	mov	mc16ul,mcnt16u
000042 24aa      	clr	mc16uh
000043 d017      	rcall	div16u
         	
000044 2c9b      	mov	mc16ul,m16ua
000045 2cac      	mov	mc16uh,m16ub
000046 e052      	ldi	mcnt16u,2
000047 2eb5      	mov	mp16ul,mcnt16u
000048 24cc      	clr	mp16uh
000049 d002      	rcall	mpy16u
         	
00004a 0000      	nop
00004b 0000      	nop
         
00004c 24ee      mpy16u:	clr	m16u3		;清2.3
00004d 24dd      	clr	m16u2
00004e e150      	ldi	mcnt16u,16	;
00004f 94c6      	lsr	mp16uH
000050 94b7      	ror	mp16uL
000051 f410      m16u_1:	brcc	noad8		;C清零转
000052 0cd9      	add	m16u2,mc16uL	;加被乘数到2
000053 1cea      	adc	m16u3,mc16uH	;加被乘数到3
000054 94e7      noad8:	ror	m16u3		;带进位右循环
000055 94d7      	ror	m16u2		;带进位右循环
000056 94c7      	ror	m16ub		;带进位右循环
000057 94b7      	ror	m16ua		;带进位右循环
000058 955a      	dec	mcnt16u		;计数减1
000059 f7b9      	brne	m16u_1		;不为零转
00005a 9508      	ret
         
          .def	drem16uL=r13		;余数  低位
          .def	drem16uH=r14		;余数  高位
          .def	dres16uL=r11		;  商  低位
          .def	dres16uH=r12		;  商  高位
          .def	dd16uL	=r11		;被除数 低位
          .def	dd16uH	=r12		;被除数 高位
          .def	dv16uL	=r9		;除数   低位
          .def	dv16uH	=r10		;除数   高位
          .def	dcnt16u	=r21		
         
         ;***** Code
         
00005b 24dd      div16u:	clr	drem16uL		;清除余数低位
00005c 18ee      	sub	drem16uH,drem16uH	;清除余数高位
00005d e151      	ldi	dcnt16u,17		;循环计数
00005e 1cbb      d16u_1:	rol	dd16uL			;带进位左移
00005f 1ccc      	rol	dd16uH
000060 955a      	dec	dcnt16u			;decrement counter
000061 f409      	brne	d16u_2			;不为0转
000062 9508      	ret				;return
000063 1cdd      d16u_2:	rol	drem16uL		;shift dividend into remainder
000064 1cee      	rol	drem16uH
000065 18d9      	sub	drem16uL,dv16uL		;remainder = remainder - divisor
000066 08ea      	sbc	drem16uH,dv16uH	;
000067 f420      	brcc	d16u_3			;if result negative
000068 0cd9      	add	drem16uL,dv16uL		;restore remainder
000069 1cea      	adc	drem16uH,dv16uH
00006a 9488      	clc				;clear carry to be shifted into result
00006b cff2      	rjmp	d16u_1			;else
00006c 9408      d16u_3:	sec				;set carry to be shifted into result
00006d cff0      	rjmp	d16u_1
Assembly complete with no errors.

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