📄 model.h
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/*************************************************************************************/
//
// Config CODEC control registers
//
/*************************************************************************************/
#include "CODEC_H"
#include "main.h"
#include <csl_dma.h>
#include <csl_i2c.h>
#include <csl_emif.h>
#include <csl_mcbsp.h>
#undef CODEC_ADDR
#define CODEC_ADDR 0x1A
// 数字音频接口格式设置
// AIC23为主模式,数据为I2S模式,数据长度16位
Uint16 Digital_Audio_Inteface_Format[2]={
Codec_DAIF_REV,
DAIF_MS(1)+DAIF_LRSWAP(0)+DAIF_LRP(0)+DAIF_IWL(0)+DAIF_FOR(2)};
// AIC23的波特率设置,采样率为8k,CLKIN=CLKOUT=MCLK
// 时钟模式设为普通模式,基过采样率为250Fs
Uint16 Sample_Rate_Control[2] = {
Codec_SRC_REV,
SRC_CLKIN(0)+SRC_CLKOUT(0)+SRC_SR(3)+SRC_BOSR(0)+SRC_USB(0)};
// AIC23寄存器复位
Uint16 Reset[2] ={
Codec_RST_REV,
RST_RES};
// AIC23节电方式设置，所有部分均处于工作状态
Uint16 Power_Down_Control[2] ={
Codec_PDC_REV,
PDC_DEFAULT};
// AIC23模拟音频的控制:关掉侧音
// DAC使能,ADC输入选择为音频输入
Uint16 Analog_Aduio_Path_Control[2] = {
Codec_AAPC_STA2(0),
AAPC_STA10(0)+AAPC_STE(0)+AAPC_DAC(1)+AAPC_BYP(0)+AAPC_INSEL(0)+AAPC_MICM(0)+AAPC_MICB(1)};
// AIC23数字音频通路的控制
// 使能ADC高通滤波
Uint16 Digital_Audio_Path_Control[2] ={
Codec_DAPC_REV,
DAPC_DACM(0)+DAPC_DEEMP(0)+DAPC_ADCHP(1)};
// AIC23数字接口的使能
Uint16 Digital_Interface_Activation[2] ={
Codec_DIA_REV,
DIA_ACT(1)};
// AIC23左通路音频调节
Uint16 Left_Line_Input_Volume_Control[2] ={
Codec_LLIVC_LPS(0),
LLIVC_LIM(0)+LLIVC_LIV(31)};
// AIC23右通路音频调节
Uint16 Right_Line_Input_Volume_Control[2] = {
Codec_RLIVC_RLS(0),
RLIVC_RIM(0)+RLIVC_RIV(31)};
// AIC23耳机左通路音频调节
Uint16 Left_Headphone_Volume_Control[2] = {
Codec_LHPVC_LRS(0),
LHPVC_LZC(0)+LHPVC_LHV(127)};
// AIC23耳机右通路音频调节
Uint16 Right_Headphone_Volume_Control[2] = {
Codec_RHPVC_RLS(0),
LHPVC_RZC(0)+LHPVC_RHV(127)};
/* 声明CSL库初始化、USB和定时器中断配置函数*/
void Csl_Config(void);
void Codec_Config(void);
void codec_sample_rate(unsigned int sample);
void Mcbsp_Config(void);
void MyDma_Config(void);
unsigned int sysreg_read(unsigned int port);
void SysInt_Enable();
void sysint_disable(unsigned int setdata);
void USB_Command_Write(unsigned int regdata);
unsigned int USB_Command_Read(void);
BOOL SX2_FifoWriteSingle(long int channel, int value);
unsigned int SX2_FifoReadSingle(long int channel);
/***************************************************************************************/
//
// Config I2C: Use I2C to interface CODEC control interface
//
/***************************************************************************************/
I2C_Setup Setup = {
0, // 7 bit address mode
0x0000, // own address
100, // clkout value (Mhz)
400, // a number between 10 and 400
0, // 8 bits/byte to be received or transmitted
0, // DLB mode off
0 // FREE mode on
};
/****************************************************************************************/
//
// Config McBSP: Use McBSP to send and receive the data between DSP and AIC23B
//
/****************************************************************************************/
MCBSP_Config Mcbsp1Config = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, // DLB = 0
MCBSP_SPCR1_RJUST_RZF, // RJUST = 0,right justify the data and zero fill the MSBs
MCBSP_SPCR1_CLKSTP_DISABLE, // CLKSTP = 0
MCBSP_SPCR1_DXENA_OFF, // DXENA = 1,DX delay enabler on
0, // Reserved = 0
MCBSP_SPCR1_RINTM_RRDY, // RINTM = 0
MCBSP_SPCR1_RSYNCERR_NO, // RSYNCER = 0
MCBSP_SPCR1_RFULL_NO, // RFULL = 0
MCBSP_SPCR1_RRDY_NO, // RRDY = 0
MCBSP_SPCR1_RRST_DISABLE // RRST = 0; Disable receiver
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, // FREE = 0
MCBSP_SPCR2_SOFT_NO, // SOFT = 0
MCBSP_SPCR2_FRST_RESET, // FRST = 0 ; Disable the frame-sync logic
MCBSP_SPCR2_GRST_RESET, // GRST = 0 ; The sample rate generator is in its reset state
MCBSP_SPCR2_XINTM_XRDY, // XINTM = 0
MCBSP_SPCR2_XSYNCERR_NO, // XSYNCER =0
MCBSP_SPCR2_XEMPTY_NO, // XEMPTY = 0
MCBSP_SPCR2_XRDY_NO, // XRDY = 0
MCBSP_SPCR2_XRST_DISABLE // XRST = 0 Disable transimitter
),
// 单数据相，接受数据长度为16位,每相2个数据
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(1), // RFRLEN1 = 1
MCBSP_RCR1_RWDLEN1_16BIT // RWDLEN1 = 2
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, // RPHASE = 0
MCBSP_RCR2_RFRLEN2_OF(1), // RFRLEN2 = 0
MCBSP_RCR2_RWDLEN2_16BIT, // RWDLEN2 = 2
MCBSP_RCR2_RCOMPAND_MSB, // RCOMPAND = 0 No companding,any size data, MSB received first
MCBSP_RCR2_RFIG_NO, // RFIG = 1 Frame-sync ignore
MCBSP_RCR2_RDATDLY_1BIT // RDATDLY = 1 1-bit data delay
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(1), // XFRLEN1 = 1
MCBSP_XCR1_XWDLEN1_16BIT // XWDLEN1 = 2
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, // XPHASE = 0
MCBSP_XCR2_XFRLEN2_OF(1), // XFRLEN2 = 0
MCBSP_XCR2_XWDLEN2_16BIT, // XWDLEN2 = 2
MCBSP_XCR2_XCOMPAND_MSB, // XCOMPAND = 0
MCBSP_XCR2_XFIG_NO, // XFIG = 1 Unexpected Frame-sync ignore
MCBSP_XCR2_XDATDLY_1BIT // XDATDLY = 1 1-bit data delay
),
MCBSP_SRGR1_DEFAULT,
MCBSP_SRGR2_DEFAULT,
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET, // IDLEEN = 0
MCBSP_PCR_XIOEN_SP, // XIOEN = 0
MCBSP_PCR_RIOEN_SP, // RIOEN = 0
MCBSP_PCR_FSXM_EXTERNAL, // FSXM = 0 Tranmit frame-syn is provided by AIC23B
MCBSP_PCR_FSRM_EXTERNAL, // FSRM = 0 Receive frame-syn is provided by AIC23B
MCBSP_PCR_CLKXM_INPUT, // CLKR is input
MCBSP_PCR_CLKRM_INPUT, // CLKX is input
MCBSP_PCR_SCLKME_NO, // SCLKME=0 CLKG is taken from the McBSP internal input clock
MCBSP_PCR_CLKSSTAT_0, // The signal on the CLKS pin is low
MCBSP_PCR_DXSTAT_0, // Drive the signal on the DX pin low
MCBSP_PCR_DRSTAT_0, // The signal on the DR pin is low
MCBSP_PCR_FSXP_ACTIVEHIGH, // FSXP = 1 Because a falling edge on LRCIN or LRCOUT starts data transfer
MCBSP_PCR_FSRP_ACTIVELOW, // FSRP = 1
MCBSP_PCR_CLKXP_FALLING, // CLKXP = 1 The falling edge of BCLK starts data transfer
MCBSP_PCR_CLKRP_RISING // CLKRP = 0
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
// 定义McBSP的句柄
MCBSP_Handle hMcbsp;
/********************************************************************************************/
//
// DMA configration struction
//
/********************************************************************************************/
DMA_Config MyConfig = {
DMA_DMACSDP_RMK( /* Source and destination parameters register */
DMA_DMACSDP_DSTBEN_NOBURST, // Bursting disabled (single access enabled) at the destination
DMA_DMACSDP_DSTPACK_OFF, // Packing disabled at the destination
DMA_DMACSDP_DST_DARAM, // DARAM via internal memory port 1
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_EMIF, // DMA_DMACSDP_SRC_EMIF
DMA_DMACSDP_DATATYPE_16BIT
),
DMA_DMACCR_RMK( /* Channel control register */
DMA_DMACCR_DSTAMODE_POSTINC, // Automatic post increment
DMA_DMACCR_SRCAMODE_POSTINC,
DMA_DMACCR_ENDPROG_OFF, // Configuration registers ready for programming / Programming in progress
DMA_DMACCR_REPEAT_OFF, // Repeat only if ENDPROG = 1
DMA_DMACCR_AUTOINIT_OFF, // Auto-initialization is disabled
DMA_DMACCR_EN_STOP, // Channel is disabled
DMA_DMACCR_PRIO_HI, // High priority
DMA_DMACCR_FS_ENABLE, // Frame synchronization
DMA_DMACCR_SYNC_NONE // No synchronization event 这个得改成什么同步?
),
DMA_DMACICR_RMK( /* Interrupt control register */
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
),
(DMA_AdrPtr) &codecdat, /* DMA Channel Source Start Address (Lower Bits) */
0, /* DMA Channel Source Start Address (Upper Bits) */
(DMA_AdrPtr)&epdataw, /* DMA Channel Source Destination Address(Lower Bits) */
0, /* DMA Channel Source Destination Address (Upper Bits) */
400, /* Channel Element Number Register */
1, /* Channel Frame Number Register */
0, /* DMA Channel Source Frame Index Register */
0, /* DMA Channel Source Element Index Register */
0, /* DMA Channel Destination Frame Index Register */
0 /* DMA Channel Destination Element Index */
};
/****************************************************************************************/
//
// Config EMIF: Use emif to access control and data interface of USB
//
/****************************************************************************************/
EMIF_Config MyEmifConfig = {
EMIF_GBLCTL1_RMK( // EMIF Global Control Register 1
EMIF_GBLCTL1_NOHOLD_HOLD_ENABLED, // Hold enable
EMIF_GBLCTL2_EK2HZ_HIGHZ, // EMIF_GBLCTL1_EK1HZ_EK1ENHigh-Z control
EMIF_GBLCTL1_EK1EN_ENABLED // ECLKOUT1 Enable
),
EMIF_GBLCTL2_RMK( // EMIF Global Control Register 2
EMIF_GBLCTL2_EK2RATE_1XCLK, // ECLKOUT2 Rate
EMIF_GBLCTL2_EK2HZ_HIGHZ, // EMIF_GBLCTL2_EK2HZ_EK2ENEK2HZ = 0, ECLKOUT2 is driven with value specified by EKnEN during
EMIF_GBLCTL2_EK2EN_DISABLED // ECLKOUT2 Enable (enabled by default)
),
EMIF_CE1CTL1_RMK( // CE1 Space Control Register 1
EMIF_CE1CTL1_TA_OF(3), // Turn-Around time
EMIF_CE1CTL1_READ_STROBE_OF(6), // Read strobe width
EMIF_CE1CTL1_MTYPE_16BIT_ASYNC, // Access type
EMIF_CE1CTL1_WRITE_HOLD_MSB_LOW, // Write hold width MSB bit
EMIF_CE1CTL1_READ_HOLD_OF(3) // Read hold width
),
EMIF_CE1CTL2_RMK( // CE1 Space Control Register 2
EMIF_CE1CTL2_WRITE_SETUP_OF(2), // Write setup width
EMIF_CE1CTL2_WRITE_STROBE_OF(6), // Write strobe width
EMIF_CE1CTL2_WRITE_HOLD_OF(8), // Write hold width
EMIF_CE1CTL2_READ_SETUP_OF(2) // Read setup width
),
EMIF_CE0CTL1_RMK( // CE0 Space Control Register 1
EMIF_CE0CTL1_TA_DEFAULT,
EMIF_CE0CTL1_READ_STROBE_DEFAULT,
EMIF_CE0CTL1_MTYPE_DEFAULT,
EMIF_CE0CTL1_WRITE_HOLD_MSB_DEFAULT,
EMIF_CE0CTL1_READ_HOLD_DEFAULT
),
EMIF_CE0CTL2_RMK( // CE0 Space Control Register 2
EMIF_CE0CTL2_WRITE_SETUP_DEFAULT,
EMIF_CE0CTL2_WRITE_STROBE_DEFAULT,
EMIF_CE0CTL2_WRITE_HOLD_DEFAULT,
EMIF_CE0CTL2_READ_SETUP_DEFAULT
),
EMIF_CE2CTL1_RMK( // CE2 Space Control Register 1
EMIF_CE2CTL1_TA_DEFAULT, // Not use for SDRAM (asynchronous memory types only)
EMIF_CE2CTL1_READ_STROBE_DEFAULT, // Read strobe width
EMIF_CE2CTL1_MTYPE_32BIT_SDRAM, // 32-bit-wide SDRAM
EMIF_CE2CTL1_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE2CTL1_READ_HOLD_DEFAULT // Read hold width
),
EMIF_CE2CTL2_RMK( // CE2 Space Control Register 2
EMIF_CE2CTL2_WRITE_SETUP_DEFAULT, // Write setup width
EMIF_CE2CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
EMIF_CE2CTL2_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE2CTL2_READ_SETUP_DEFAULT // Read setup width
),
EMIF_CE3CTL1_RMK( // CE3 Space Control Register 1
EMIF_CE3CTL1_TA_DEFAULT, // Not use for SDRAM (asynchronous memory types only)
EMIF_CE3CTL1_READ_STROBE_DEFAULT, // Read strobe width
EMIF_CE2CTL1_MTYPE_32BIT_SDRAM, // 32-bit-wide SDRAM
EMIF_CE3CTL1_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL1_READ_HOLD_DEFAULT // Read hold width
),
EMIF_CE3CTL2_RMK( // CE3 Space Control Register 2
EMIF_CE3CTL2_WRITE_SETUP_DEFAULT, // Write setup width
EMIF_CE3CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
EMIF_CE3CTL2_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL2_READ_SETUP_DEFAULT // Read setup width
),
EMIF_SDCTL1_RMK( // SDRAM Control Register 1
EMIF_SDCTL1_TRC_OF(6), // Specifies tRC value of the SDRAM in EMIF clock cycles.
EMIF_SDCTL1_SLFRFR_DISABLED // Auto-refresh mode
),
EMIF_SDCTL2_RMK( // SDRAM Control Register 2
0x11, // 4 banks,11 row address, 8 column address
EMIF_SDCTL2_RFEN_ENABLED, // Refresh enabled
EMIF_SDCTL2_INIT_INIT_SDRAM,
EMIF_SDCTL2_TRCD_OF(1), // Specifies tRCD value of the SDRAM in EMIF clock cycles
EMIF_SDCTL2_TRP_OF(1) // Specifies tRP value of the SDRAM in EMIF clock cycles
),
0x61B, // SDRAM Refresh Control Register 1
0x0300, // SDRAM Refresh Control Register 2
EMIF_SDEXT1_RMK( // SDRAM Extension Register 1
EMIF_SDEXT1_R2WDQM_1CYCLE,
EMIF_SDEXT1_RD2WR_3CYCLES,
EMIF_SDEXT1_RD2DEAC_1CYCLE,
EMIF_SDEXT1_RD2RD_1CYCLE,
EMIF_SDEXT1_THZP_OF(1), // tPROZ2=2
EMIF_SDEXT1_TWR_OF(0), //
EMIF_SDEXT1_TRRD_2CYCLES,
EMIF_SDEXT1_TRAS_OF(4),
EMIF_SDEXT1_TCL_2CYCLES
),
EMIF_SDEXT2_RMK( // SDRAM Extension Register 2
EMIF_SDEXT2_WR2RD_0CYCLES,
EMIF_SDEXT2_WR2DEAC_1CYCLE,
0,
EMIF_SDEXT2_R2WDQM_1CYCLE
),
EMIF_CE1SEC1_DEFAULT, // CE1 Secondary Control Register 1
EMIF_CE0SEC1_DEFAULT, // CE0 Secondary Control Register 1
EMIF_CE2SEC1_DEFAULT, // CE2 Secondary Control Register 1
EMIF_CE3SEC1_DEFAULT, // CE3 Secondary Control Register 1
EMIF_CESCR_DEFAULT // CE Size Control Register
};
//******************************************************************************//
// No more
//******************************************************************************//
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