x86.md

LCC4.2 C编译器源码

stmt: ASGNF8(VREGP,reg)  "# write register\n"
stmt: ASGNI8(VREGP,reg)  "# write register\n"
stmt: ASGNP8(VREGP,reg)  "# write register\n"
stmt: ASGNU8(VREGP,reg)  "# write register\n"
con: CNSTI1  "%a"
con: CNSTU1  "%a"

con: CNSTI2  "%a"
con: CNSTU2  "%a"

con: CNSTI4  "%a"
con: CNSTU4  "%a"
con: CNSTP4  "%a"

con: CNSTI8  "%a"
con: CNSTU8  "%a"
con: CNSTP8  "%a"
stmt: reg  ""
acon: ADDRGP4  "(%a)"
acon: con     "(%0)"
base: ADDRGP4          "(%a)"
base: reg              "[%0]"
base: ADDI4(reg,acon)  "%1[%0]"
base: ADDP4(reg,acon)  "%1[%0]"
base: ADDU4(reg,acon)  "%1[%0]"
base: ADDRFP4  "(%a)[ebp]"
base: ADDRLP4  "(%a)[ebp]"
index: reg "%0"
index: LSHI4(reg,con1)  "%0*2"
index: LSHI4(reg,con2)  "%0*4"
index: LSHI4(reg,con3)  "%0*8"

con1:  CNSTI4  "1"  range(a, 1, 1)
con1:  CNSTU4  "1"  range(a, 1, 1)
con2:  CNSTI4  "2"  range(a, 2, 2)
con2:  CNSTU4  "2"  range(a, 2, 2)
con3:  CNSTI4  "3"  range(a, 3, 3)
con3:  CNSTU4  "3"  range(a, 3, 3)
index: LSHU4(reg,con1)  "%0*2"
index: LSHU4(reg,con2)  "%0*4"
index: LSHU4(reg,con3)  "%0*8"
addr: base              "%0"
addr: ADDI4(index,base)  "%1[%0]"
addr: ADDP4(index,base)  "%1[%0]"
addr: ADDU4(index,base)  "%1[%0]"
addr: index  "[%0]"
mem: INDIRI1(addr)  "byte ptr %0"
mem: INDIRI2(addr)  "word ptr %0"
mem: INDIRI4(addr)  "dword ptr %0"
mem: INDIRU1(addr)  "byte ptr %0"
mem: INDIRU2(addr)  "word ptr %0"
mem: INDIRU4(addr)  "dword ptr %0"
mem: INDIRP4(addr)  "dword ptr %0"
rc:   reg  "%0"
rc:   con  "%0"

mr:   reg  "%0"
mr:   mem  "%0"

mrc0: mem  "%0"
mrc0: rc   "%0"
mrc1: mem  "%0"  1
mrc1: rc   "%0"

mrc3: mem  "%0"  3
mrc3: rc   "%0"
reg: addr         "lea %c,%0\n"  1
reg: mrc0         "mov %c,%0\n"  1
reg: LOADI1(reg)  "# move\n"  1
reg: LOADI2(reg)  "# move\n"  1
reg: LOADI4(reg)  "# move\n"  move(a)
reg: LOADU1(reg)  "# move\n"  1
reg: LOADU2(reg)  "# move\n"  1
reg: LOADU4(reg)  "# move\n"  move(a)
reg: LOADP4(reg)  "# move\n"  move(a)
reg: ADDI4(reg,mrc1)  "?mov %c,%0\nadd %c,%1\n"  1
reg: ADDP4(reg,mrc1)  "?mov %c,%0\nadd %c,%1\n"  1
reg: ADDU4(reg,mrc1)  "?mov %c,%0\nadd %c,%1\n"  1
reg: SUBI4(reg,mrc1)  "?mov %c,%0\nsub %c,%1\n"  1
reg: SUBP4(reg,mrc1)  "?mov %c,%0\nsub %c,%1\n"  1
reg: SUBU4(reg,mrc1)  "?mov %c,%0\nsub %c,%1\n"  1
reg: BANDI4(reg,mrc1)  "?mov %c,%0\nand %c,%1\n"  1
reg: BORI4(reg,mrc1)   "?mov %c,%0\nor %c,%1\n"   1
reg: BXORI4(reg,mrc1)  "?mov %c,%0\nxor %c,%1\n"  1
reg: BANDU4(reg,mrc1)  "?mov %c,%0\nand %c,%1\n"  1
reg: BORU4(reg,mrc1)   "?mov %c,%0\nor %c,%1\n"   1
reg: BXORU4(reg,mrc1)  "?mov %c,%0\nxor %c,%1\n"  1
stmt: ASGNI4(addr,ADDI4(mem,con1))  "inc %1\n"  memop(a)
stmt: ASGNI4(addr,ADDU4(mem,con1))  "inc %1\n"  memop(a)
stmt: ASGNP4(addr,ADDP4(mem,con1))  "inc %1\n"  memop(a)
stmt: ASGNI4(addr,SUBI4(mem,con1))  "dec %1\n"  memop(a)
stmt: ASGNI4(addr,SUBU4(mem,con1))  "dec %1\n"  memop(a)
stmt: ASGNP4(addr,SUBP4(mem,con1))  "dec %1\n"  memop(a)
stmt: ASGNI4(addr,ADDI4(mem,rc))   "add %1,%2\n"  memop(a)
stmt: ASGNI4(addr,SUBI4(mem,rc))   "sub %1,%2\n"  memop(a)
stmt: ASGNU4(addr,ADDU4(mem,rc))   "add %1,%2\n"  memop(a)
stmt: ASGNU4(addr,SUBU4(mem,rc))   "sub %1,%2\n"  memop(a)

stmt: ASGNI4(addr,BANDI4(mem,rc))  "and %1,%2\n"  memop(a)
stmt: ASGNI4(addr,BORI4(mem,rc))   "or %1,%2\n"   memop(a)
stmt: ASGNI4(addr,BXORI4(mem,rc))  "xor %1,%2\n"  memop(a)
stmt: ASGNU4(addr,BANDU4(mem,rc))  "and %1,%2\n"  memop(a)
stmt: ASGNU4(addr,BORU4(mem,rc))   "or %1,%2\n"   memop(a)
stmt: ASGNU4(addr,BXORU4(mem,rc))  "xor %1,%2\n"  memop(a)
reg: BCOMI4(reg)  "?mov %c,%0\nnot %c\n"  2
reg: BCOMU4(reg)  "?mov %c,%0\nnot %c\n"  2
reg: NEGI4(reg)   "?mov %c,%0\nneg %c\n"  2

stmt: ASGNI4(addr,BCOMI4(mem))  "not %1\n"  memop(a)
stmt: ASGNU4(addr,BCOMU4(mem))  "not %1\n"  memop(a)
stmt: ASGNI4(addr,NEGI4(mem))   "neg %1\n"  memop(a)
reg: LSHI4(reg,con5)  "?mov %c,%0\nsal %c,%1\n"  2
reg: LSHU4(reg,con5)  "?mov %c,%0\nshl %c,%1\n"  2
reg: RSHI4(reg,con5)  "?mov %c,%0\nsar %c,%1\n"  2
reg: RSHU4(reg,con5)  "?mov %c,%0\nshr %c,%1\n"  2

stmt: ASGNI4(addr,LSHI4(mem,con5))  "sal %1,%2\n"  memop(a)
stmt: ASGNI4(addr,LSHU4(mem,con5))  "shl %1,%2\n"  memop(a)
stmt: ASGNI4(addr,RSHI4(mem,con5))  "sar %1,%2\n"  memop(a)
stmt: ASGNI4(addr,RSHU4(mem,con5))  "shr %1,%2\n"  memop(a)

con5: CNSTI4  "%a"  range(a, 0, 31)

reg: LSHI4(reg,reg)  "?mov %c,%0\nmov ecx,%1\nsal %c,cl\n"  3
reg: LSHU4(reg,reg)  "?mov %c,%0\nmov ecx,%1\nshl %c,cl\n"  2
reg: RSHI4(reg,reg)  "?mov %c,%0\nmov ecx,%1\nsar %c,cl\n"  2
reg: RSHU4(reg,reg)  "?mov %c,%0\nmov ecx,%1\nshr %c,cl\n"  2
reg: MULI4(reg,mrc3)  "?mov %c,%0\nimul %c,%1\n"  14
reg: MULI4(con,mr)    "imul %c,%1,%0\n"  13
reg: MULU4(reg,mr)  "mul %1\n"  13
reg: DIVU4(reg,reg)  "xor edx,edx\ndiv %1\n"
reg: MODU4(reg,reg)  "xor edx,edx\ndiv %1\n"
reg: DIVI4(reg,reg)  "cdq\nidiv %1\n"
reg: MODI4(reg,reg)  "cdq\nidiv %1\n"
reg: CVPU4(reg)  "mov %c,%0\n"  move(a)
reg: CVUP4(reg)  "mov %c,%0\n"  move(a)
reg: CVII4(INDIRI1(addr))  "movsx %c,byte ptr %0\n"  3
reg: CVII4(INDIRI2(addr))  "movsx %c,word ptr %0\n"  3
reg: CVUU4(INDIRU1(addr))  "movzx %c,byte ptr %0\n"  3
reg: CVUU4(INDIRU2(addr))  "movzx %c,word ptr %0\n"  3
reg: CVII4(reg)  "# extend\n"  3
reg: CVIU4(reg)  "# extend\n"  3
reg: CVUI4(reg)  "# extend\n"  3
reg: CVUU4(reg)  "# extend\n"  3

reg: CVII1(reg)  "# truncate\n"  1
reg: CVII2(reg)  "# truncate\n"  1
reg: CVUU1(reg)  "# truncate\n"  1
reg: CVUU2(reg)  "# truncate\n"  1
stmt: ASGNI1(addr,rc)  "mov byte ptr %0,%1\n"   1
stmt: ASGNI2(addr,rc)  "mov word ptr %0,%1\n"   1
stmt: ASGNI4(addr,rc)  "mov dword ptr %0,%1\n"  1
stmt: ASGNU1(addr,rc)  "mov byte ptr %0,%1\n"   1
stmt: ASGNU2(addr,rc)  "mov word ptr %0,%1\n"   1
stmt: ASGNU4(addr,rc)  "mov dword ptr %0,%1\n"  1
stmt: ASGNP4(addr,rc)  "mov dword ptr %0,%1\n"  1
stmt: ARGI4(mrc3)  "push %0\n"  1
stmt: ARGU4(mrc3)  "push %0\n"  1
stmt: ARGP4(mrc3)  "push %0\n"  1
stmt: ASGNB(reg,INDIRB(reg))  "mov ecx,%a\nrep movsb\n"
stmt: ARGB(INDIRB(reg))  "# ARGB\n"
memf: INDIRF8(addr)         "qword ptr %0"
memf: INDIRF4(addr)         "dword ptr %0"
memf: CVFF8(INDIRF4(addr))  "dword ptr %0"
reg: memf  "fld %0\n"  3
stmt: ASGNF8(addr,reg)         "fstp qword ptr %0\n"  7
stmt: ASGNF4(addr,reg)         "fstp dword ptr %0\n"  7
stmt: ASGNF4(addr,CVFF4(reg))  "fstp dword ptr %0\n"  7
stmt: ARGF8(reg)  "sub esp,8\nfstp qword ptr [esp]\n"
stmt: ARGF4(reg)  "sub esp,4\nfstp dword ptr [esp]\n"
reg: NEGF8(reg)  "fchs\n"
reg: NEGF4(reg)  "fchs\n"
flt: memf  " %0"
flt: reg   "p st(1),st"
reg: ADDF8(reg,flt)  "fadd%1\n"
reg: ADDF4(reg,flt)  "fadd%1\n"
reg: DIVF8(reg,flt)  "fdiv%1\n"
reg: DIVF4(reg,flt)  "fdiv%1\n"
reg: MULF8(reg,flt)  "fmul%1\n"
reg: MULF4(reg,flt)  "fmul%1\n"
reg: SUBF8(reg,flt)  "fsub%1\n"
reg: SUBF4(reg,flt)  "fsub%1\n"
reg: CVFF8(reg)  "# CVFF8\n"
reg: CVFF4(reg)  "sub esp,4\nfstp dword ptr 0[esp]\nfld dword ptr 0[esp]\nadd esp,4\n"  12

reg: CVFI4(reg)  "call __ftol\n" 31
reg: CVIF8(INDIRI4(addr))  "fild dword ptr %0\n"  10
reg: CVIF4(reg)  "push %0\nfild dword ptr 0[esp]\nadd esp,4\n"  12

reg: CVIF8(reg)  "push %0\nfild dword ptr 0[esp]\nadd esp,4\n"  12

addrj: ADDRGP4  "%a"
addrj: reg      "%0"  2
addrj: mem      "%0"  2

stmt:  JUMPV(addrj)  "jmp %0\n"  3
stmt:  LABELV        "%a:\n"
stmt: EQI4(mem,rc)  "cmp %0,%1\nje %a\n"   5
stmt: GEI4(mem,rc)  "cmp %0,%1\njge %a\n"  5
stmt: GTI4(mem,rc)  "cmp %0,%1\njg %a\n"   5
stmt: LEI4(mem,rc)  "cmp %0,%1\njle %a\n"  5
stmt: LTI4(mem,rc)  "cmp %0,%1\njl %a\n"   5
stmt: NEI4(mem,rc)  "cmp %0,%1\njne %a\n"  5
stmt: GEU4(mem,rc)  "cmp %0,%1\njae %a\n"  5
stmt: GTU4(mem,rc)  "cmp %0,%1\nja  %a\n"  5
stmt: LEU4(mem,rc)  "cmp %0,%1\njbe %a\n"  5
stmt: LTU4(mem,rc)  "cmp %0,%1\njb  %a\n"  5
stmt: EQI4(reg,mrc1)  "cmp %0,%1\nje %a\n"   4
stmt: GEI4(reg,mrc1)  "cmp %0,%1\njge %a\n"  4
stmt: GTI4(reg,mrc1)  "cmp %0,%1\njg %a\n"   4
stmt: LEI4(reg,mrc1)  "cmp %0,%1\njle %a\n"  4
stmt: LTI4(reg,mrc1)  "cmp %0,%1\njl %a\n"   4
stmt: NEI4(reg,mrc1)  "cmp %0,%1\njne %a\n"  4

stmt: EQU4(reg,mrc1)  "cmp %0,%1\nje %a\n"   4
stmt: GEU4(reg,mrc1)  "cmp %0,%1\njae %a\n"  4
stmt: GTU4(reg,mrc1)  "cmp %0,%1\nja %a\n"   4
stmt: LEU4(reg,mrc1)  "cmp %0,%1\njbe %a\n"  4
stmt: LTU4(reg,mrc1)  "cmp %0,%1\njb %a\n"   4
stmt: NEU4(reg,mrc1)  "cmp %0,%1\njne %a\n"  4
cmpf: memf  " %0"
cmpf: reg   "p"
stmt: EQF8(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %b\nje %a\n%b:\n"
stmt: GEF8(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njbe %a\n"
stmt: GTF8(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njb %a\n"
stmt: LEF8(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njae %a\n"
stmt: LTF8(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\nja %a\n"
stmt: NEF8(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njne %a\n"

stmt: EQF4(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %b\nje %a\n%b:\n"
stmt: GEF4(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njbe %a\n\n"
stmt: GTF4(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njb %a\n"
stmt: LEF4(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njae %a\n\n"
stmt: LTF4(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\nja %a\n"
stmt: NEF4(cmpf,reg)  "fcomp%0\nfstsw ax\nsahf\njp %a\njne %a\n"
reg:  CALLI4(addrj)  "call %0\nadd esp,%a\n"
reg:  CALLU4(addrj)  "call %0\nadd esp,%a\n"
reg:  CALLP4(addrj)  "call %0\nadd esp,%a\n"
stmt: CALLV(addrj)   "call %0\nadd esp,%a\n"
reg: CALLF4(addrj)  "call %0\nadd esp,%a\n"
reg: CALLF8(addrj)  "call %0\nadd esp,%a\n"
stmt: CALLF4(addrj)  "call %0\nadd esp,%a\nfstp\n"
stmt: CALLF8(addrj)  "call %0\nadd esp,%a\nfstp\n"

stmt: RETI4(reg)  "# ret\n"
stmt: RETU4(reg)  "# ret\n"
stmt: RETP4(reg)  "# ret\n"
stmt: RETF4(reg)  "# ret\n"
stmt: RETF8(reg)  "# ret\n"
%%
static void progbeg(int argc, char *argv[]) {
        int i;

        {
                union {
                        char c;
                        int i;
                } u;
                u.i = 0;
                u.c = 1;
                swap = ((int)(u.i == 1)) != IR->little_endian;
        }
        parseflags(argc, argv);
        intreg[EAX] = mkreg("eax", EAX, 1, IREG);
        intreg[EDX] = mkreg("edx", EDX, 1, IREG);
        intreg[ECX] = mkreg("ecx", ECX, 1, IREG);
        intreg[EBX] = mkreg("ebx", EBX, 1, IREG);
        intreg[ESI] = mkreg("esi", ESI, 1, IREG);
        intreg[EDI] = mkreg("edi", EDI, 1, IREG);

        shortreg[EAX] = mkreg("ax", EAX, 1, IREG);
        shortreg[ECX] = mkreg("cx", ECX, 1, IREG);
        shortreg[EDX] = mkreg("dx", EDX, 1, IREG);
        shortreg[EBX] = mkreg("bx", EBX, 1, IREG);
        shortreg[ESI] = mkreg("si", ESI, 1, IREG);
        shortreg[EDI] = mkreg("di", EDI, 1, IREG);

        charreg[EAX]  = mkreg("al", EAX, 1, IREG);
        charreg[ECX]  = mkreg("cl", ECX, 1, IREG);
        charreg[EDX]  = mkreg("dl", EDX, 1, IREG);
        charreg[EBX]  = mkreg("bl", EBX, 1, IREG);
        for (i = 0; i < 8; i++)
                fltreg[i] = mkreg("%d", i, 0, FREG);
        charregw = mkwildcard(charreg);
        shortregw = mkwildcard(shortreg);
        intregw = mkwildcard(intreg);
        fltregw = mkwildcard(fltreg);

        tmask[IREG] = (1<<EDI) | (1<<ESI) | (1<<EBX)
                    | (1<<EDX) | (1<<ECX) | (1<<EAX);
        vmask[IREG] = 0;
        tmask[FREG] = 0xff;
        vmask[FREG] = 0;
        print(".486\n");
        print(".model flat\n");
        print("extrn __fltused:near\n");
        print("extrn __ftol:near\n");
        cseg = 0;
        quo = mkreg("eax", EAX, 1, IREG);
        quo->x.regnode->mask |= 1<<EDX;
        rem = mkreg("edx", EDX, 1, IREG);
        rem->x.regnode->mask |= 1<<EAX;
}
static Symbol rmap(int opk) {
        switch (optype(opk)) {
        case B: case P:
                return intregw;
        case I: case U:
                if (opsize(opk) == 1)
                        return charregw;
                else if (opsize(opk) == 2)
                        return shortregw;
                else
                        return intregw;
        case F:
                return fltregw;
        default:
                return 0;
        }
}
static void segment(int n) {
        if (n == cseg)
                return;
        if (cseg == CODE || cseg == LIT)
                print("_TEXT ends\n");
        else if (cseg == DATA || cseg == BSS)
                print("_DATA ends\n");
        cseg = n;
        if (cseg == CODE || cseg == LIT)
                print("_TEXT segment\n");
        else if (cseg == DATA || cseg == BSS)
                print("_DATA segment\n");
}
static void progend(void) {
        segment(0);
        print("end\n");
}