📄 adc.c
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/************************************************************************/
/* Testprogram for internal ADC */
/* running on TMS320LF2407 EVM */
/* external clock is 14.7456 MHz, PLL * 2 , CPU-Clock then 29.49 MHz */
/* date : 17.08.2000 (c) Tino Schierig */
/************************************************************************/
/* Potentiometers ( 0 to 3,3 V ) connected to ADCIN00 and ADCIN08 */
/* 8 LED's connected to Port E0...E7 ; LED-on : 1 LED off : 0 */
/* Timer GPT1 generates a 0.2second - period */
/* the period-match causes the start of the Sequencer1 */
/* ADConverter#1 : ADCin00 ADConverter#2 : ADCin08 */
/* With the EOS the ADC_ISR interrupt service routine is entered */
/* The results are read from the RESULT0 and RESULT1 registers */
/* the function show_ADC shows the last result as a light-beam on LED's */
/* program-name : F2407ADC2.c / project : F2407ADC */
/************************************************************************/
#include "regs2407.h"
/************* SETUP for the MCRA - Register **********************/
#define MCRA15 0 /* 0 : IOPB7 1 : TCLKIN */
#define MCRA14 0 /* 0 : IOPB6 1 : TDIR */
#define MCRA13 0 /* 0 : IOPB5 1 : T2PWM */
#define MCRA12 0 /* 0 : IOPB4 1 : T1PWM */
#define MCRA11 0 /* 0 : IOPB3 1 : PWM6 */
#define MCRA10 0 /* 0 : IOPB2 1 : PWM5 */
#define MCRA9 0 /* 0 : IOPB1 1 : PWM4 */
#define MCRA8 0 /* 0 : IOPB0 1 : PWM3 */
#define MCRA7 0 /* 0 : IOPA7 1 : PWM2 */
#define MCRA6 0 /* 0 : IOPA6 1 : PWM1 */
#define MCRA5 0 /* 0 : IOPA5 1 : CAP3 */
#define MCRA4 0 /* 0 : IOPA4 1 : CAP2/QEP2 */
#define MCRA3 0 /* 0 : IOPA3 1 : CAP1/QEP1 */
#define MCRA2 0 /* 0 : IOPA2 1 : XINT1 */
#define MCRA1 0 /* 0 : IOPA1 1 : SCIRXD */
#define MCRA0 0 /* 0 : IOPA0 1 : SCITXD */
/************************************************************************/
/************* SETUP for the MCRB - Register **********************/
#define MCRB9 0 /* 0 : IOPD1 1 : XINT2/EXTSOC */
#define MCRB8 1 /* 0 : CKLKOUT 1 : IOPD0 */
#define MCRB7 0 /* 0 : IOPC7 1 : CANRX */
#define MCRB6 0 /* 0 : IOPC6 1 : CANTX */
#define MCRB5 0 /* 0 : IOPC5 1 : SPISTE */
#define MCRB4 0 /* 0 : IOPC4 1 : SPICLK */
#define MCRB3 0 /* 0 : IOPC3 1 : SPISOMI */
#define MCRB2 0 /* 0 : IOPC2 1 : SPISIMO */
#define MCRB1 1 /* 0 : BIO 1 : IOPC1 */
#define MCRB0 1 /* 0 : XF 1 : IOPC0 */
/************************************************************************/
/************* SETUP for the MCRC - Register **********************/
#define MCRC13 0 /* 0 : IOPF5 1 : TCLKIN2 */
#define MCRC12 0 /* 0 : IOPF4 1 : TDIR2 */
#define MCRC11 0 /* 0 : IOPF3 1 : T4PWM/T4CMP */
#define MCRC10 0 /* 0 : IOPF2 1 : T3PWM/T3CMP */
#define MCRC9 0 /* 0 : IOPF1 1 : CAP6 */
#define MCRC8 0 /* 0 : IOPF0 1 : CAP5/QEP3 */
#define MCRC7 0 /* 0 : IOPE7 1 : CAP4/QEP2 */
#define MCRC6 0 /* 0 : IOPE6 1 : PWM12 */
#define MCRC5 0 /* 0 : IOPE5 1 : PWM11 */
#define MCRC4 0 /* 0 : IOPE4 1 : PWM10 */
#define MCRC3 0 /* 0 : IOPE3 1 : PWM9 */
#define MCRC2 0 /* 0 : IOPE2 1 : PWM8 */
#define MCRC1 0 /* 0 : IOPE1 1 : PWM7 */
#define MCRC0 0 /* 0 : IOPE0 1 : CLKOUT */
/************************************************************************/
/************* SETUP for the WDCR - Register **********************/
#define WDDIS 1 /* 0 : Watchdog enabled 1: disabled */
#define WDCHK2 1 /* 0 : System reset 1: Normal Operation */
#define WDCHK1 0 /* 0 : Normal Oper. 1: system reset */
#define WDCHK0 1 /* 0 : System reset 1: Normal Operation */
#define WDSP 7 /* Watchdog prescaler 7 : div 64 */
/************************************************************************/
/************* SETUP for the SCSR1 - Register **********************/
#define CLKSRC 0 /* 0 : intern(20MHz) */
#define LPM 0 /* 0 : Low power mode 0 if idle */
#define CLK_PS 1 /* 001 : PLL multiply by 2 */
#define ADC_CLKEN 1 /* 1 : ADC will be used in this test */
#define SCI_CLKEN 0 /* 0 : No SCI-service in this test */
#define SPI_CLKEN 0 /* 0 : No SPI-servide in this test */
#define CAN_CLKEN 0 /* 0 : No CAN-service in this test */
#define EVB_CLKEN 0 /* 0 : No EVB-Service in this test */
#define EVA_CLKEN 1 /* 1 : GPT1 period initiates ADC */
#define ILLADR 1 /* 1 : Clear ILLADR during startup */
/************************************************************************/
/************* SETUP for the ADCTRL1 - Register ********************/
#define RESET 0 /* 15 : 1 Resets entire ADC Module */
#define SOFTFREE 2 /* 13-12: 10 complete ADC before halt */
#define ACQ_PS 7 /* 11-8 : Acquisition time 16 x TCLK */
#define CPS 1 /* 7 : 1 ADC logic Clock = CLK/2 */
#define CONT_RUN 0 /* 6 : 0 No Continuous Run */
#define INT_PRI 0 /* 5 : 0 High ADC interrupt priority */
#define SEQ_CASC 0 /* 4 : 0 Dual-Sequencer mode */
#define CAL_ENA 0 /* 3 : 0 Calibration mode disabled */
#define BRG_ENA 0 /* 2 : 0 Full reference Volt. to ADC */
#define HILO 1 /* 1 : 0 VREFLO as Test Voltage */
#define STEST_ENA 0 /* 0 : 0 Self-Test mode disabled */
/************************************************************************/
/************* SETUP for the ADCTRL2 - Register ********************/
#define EVB_SOC_SEQ 0 /* 15 : 1 EVB starts Cascaded Sequ. */
#define RST_SEQ1 0 /* 14 : 1 Reset Sequencer 1 */
#define SOC_SEQ1 0 /* 13 : 0 Clears a pending SOC trig */
#define INT_ENA_SEQ1 1 /* 11-10: 1 Interrupt Mode 1 */
#define EVA_SOC_SEQ1 1 /* 8 : 1 EVA starts Sequencer1 */
#define EXT_SOC_SEQ1 0 /* 7 : 1 ADCSOC Pin starts Sequencer1 */
#define RST_SEQ2 0 /* 6 : 1 Reset Sequencer 2 */
#define SOC_SEQ2 0 /* 5 : 0 Clears a pending SOC trig */
#define INT_ENA_SEQ2 0 /* 3-2 : 0 Interrupt disabled */
#define EVB_SOC_SEQ2 0 /* 8 : 1 EVB starts Sequencer1 */
/************* SETUP for the GPTCON - Register *********************/
#define GPTCONA_T2TOADC 0 /* 10-9 : 0 no ADC-Start by GPT2-Event */
#define GPTCONA_T1TOADC 2 /* 8-7 : 2 ADC-Start by GPT1-Event */
#define GPTCONA_TCOMPOE 0 /* 6 : 0 disable all 2 GPT compare outs */
#define GPTCONA_T2PIN 0 /* 3-2 : Polar. of GPT2 comp out=forced low*/
#define GPTCONA_T1PIN 0 /* 1-0 : Pol. of GPT1 comp out=forced low */
/************************************************************************/
/************** SETUP for the T1CON - Register *********************/
#define T1CON_FREESOFT 0 /* 15-14: 0 stop on JTAG suspend */
#define T1CON_TMODE 2 /* 12-11: 2 Continuous up counting */
#define T1CON_TPS 7 /* 10-8 : 7 CPUCLK/128 */
#define T1CON_TENABLE 1 /* 6 : 1 Timer1 enable */
#define T1CON_TCLKS 0 /* 5-4 : 0 Clock source: internal */
#define T1CON_TCLD 1 /* 3-2 : 1 reload when 0 or = T1PR */
#define T1CON_TECMPR 0 /* 1 : disable timer compare */
/************************************************************************/
/************* SETUP for the WSGR - Register **********************/
#define BVIS 0 /* 10-9 : 00 Bus visibility OFF */
#define ISWS 0 /* 8 -6 : 000 0 Waitstates for IO */
#define DSWS 0 /* 5 -3 : 000 0 Waitstates data */
#define PSWS 0 /* 2 -0 : 000 0 Waitstaes code */
/************* SETUP for the IMR - Register **********************/
#define INT6 0 /* 5 : Level INT6 is masked */
#define INT5 0 /* 4 : Level INT5 is masked */
#define INT4 0 /* 3 : Level INT4 is masked */
#define INT3 0 /* 2 : Level INT3 is masked */
#define INT2 0 /* 1 : Level INT2 is masked */
#define INT1 1 /* 0 : Level INT1 is unmasked */
/************************************************************************/
#define PERIOD 46078 /* T1 PERIOD = 34ns * 128 * 46078 = 0.2s */
unsigned int ADC0_result,ADC1_result;
void c_dummy1(void)
{
while(1); /* Dummy ISR used to trap spurious interrupts */
}
void show_ADC(unsigned int result)
/* show the result of the AD-conversion on 8 LED's on Port D0-D7 */
/* the actual result is stored in ADC0_result by the ADC-ISR */
/* the result will be show as light-beam */
/* 0000 0000 00 = all LED'S off */
/* 0001 xxxx xx = LED 1 on */
/* 001x xxxx xx = LED 1+2 on */
/* 111x xxxx xx = all LED's on */
{
result>>=6;
switch(result) {
case 0 : PEDATDIR=0xFF00;break;
case 1 : PEDATDIR=0xFF01;break;
}
result>>=1;
switch(result) {
case 1 : PEDATDIR=0xFF03;break;
case 2 : PEDATDIR=0xFF07;break;
case 3 : PEDATDIR=0xFF0F;break;
case 4 : PEDATDIR=0xFF1F;break;
case 5 : PEDATDIR=0xFF3F;break;
case 6 : PEDATDIR=0xFF7F;break;
case 7 : PEDATDIR=0xFFFF;break;
}
}
interrupt void ADC_ISR(void)
{
if((PIVR-0x0004)==0) /*Verify type of interrupt ( 4 = ADC ) */
{
ADC0_result=RESULT0>>6;
ADC1_result=RESULT1>>6;
ADCTRL2 |= 0x200; /* clear ADC-Sequencer1-Interrupt flag */
MAXCONV = 1;
}
}
void main(void)
{
asm (" setc INTM"); /* Disable all interrupts */
asm (" clrc SXM"); /* Clear Sign Extension Mode bit */
asm (" clrc OVM"); /* Reset Overflow Mode bit */
asm (" clrc CNF"); /* Configure block B0 to data mem. */
WSGR=((BVIS<<9)+(ISWS<<6)+(DSWS<<3)+PSWS);
/* set the external waitstates WSGR */
WDCR=((WDDIS<<6)+(WDCHK2<<5)+(WDCHK1<<4)+(WDCHK0<<3)+WDSP);
/* Initialize Watchdog-timer */
SCSR1= ((CLKSRC<<14)+(LPM<<12)+(CLK_PS<<9)+(ADC_CLKEN<<7)+
(SCI_CLKEN<<6)+(SPI_CLKEN<<5)+(CAN_CLKEN<<4)+
(EVB_CLKEN<<3)+(EVA_CLKEN<<2)+ILLADR);
/* Initialize SCSR1 */
MCRC = ((MCRC13<<13)+(MCRC12<<12)+(MCRC11<<11)+(MCRC10<<10)
+(MCRC9<<9)+(MCRC8<<8)+(MCRC7<<7)+(MCRC6<<6)
+(MCRC5<<5)+(MCRC4<<4)+(MCRC3<<3)+(MCRC2<<2)
+(MCRC1<<1)+MCRC0);
/* Initialize master control register C */
MCRB = ((MCRB9<<9)+(MCRB8<<8)+
(MCRB7<<7)+(MCRB6<<6)+(MCRB5<<5)+(MCRB4<<4)+
(MCRB3<<3)+(MCRB2<<2)+(MCRB1<<1)+MCRB0);
/* Initialize master control register B */
MCRA = ((MCRA15<<15)+(MCRA14<<14)+(MCRA13<<13)+(MCRA12<<12)+
(MCRA11<<11)+(MCRA10<<10)+(MCRA9<<9)+(MCRA8<<8)+
(MCRA7<<7)+(MCRA6<<6)+(MCRA5<<5)+(MCRA4<<4)+
(MCRA3<<3)+(MCRA2<<2)+(MCRA1<<1)+MCRA0);
/* Initialize master control register A */
GPTCONA=((GPTCONA_T2TOADC<<9)+
(GPTCONA_T1TOADC<<7)+
(GPTCONA_TCOMPOE<<6)+
(GPTCONA_T2PIN<<2)+
(GPTCONA_T1PIN)); /* Initialize GP Timer Control */
T1PR = PERIOD; /* initialize T1-period */
T1CNT= 0x0000; /* start value for T1-counter */
T1CON=((T1CON_FREESOFT<<14)+
(T1CON_TMODE<<11)+
(T1CON_TPS<<8)+
(T1CON_TCLKS<<4)+
(T1CON_TCLD<<2)+
(T1CON_TECMPR<<1));
/* initialize Timer1 */
CALIBRATION = 0;
/* ADC-offset will be not calibrated */
MAXCONV = 1;
/* 2 subsequent conversions are performed */
/* in 1 session */
ADCTRL1 = 0x4000;
/* Master reset on the entire ADC-module */
ADCTRL1 = ((RESET<<15)+(SOFTFREE<<12)+(ACQ_PS<<8)+
(CPS<<7)+(CONT_RUN<<6)+(INT_PRI<<5)+
(SEQ_CASC<<4)+(CAL_ENA<<3)+(BRG_ENA<<2)+
(HILO<<1)+STEST_ENA);
/* Initialize ADC-module */
CHSELSEQ1 = 0x0080;
/* Channel 0 and Channel 8 are scanned */
ADCTRL2 |= 0x5000; /* clear ADC-Sequencer1-Interrupt flag */
ADCTRL2 = ((EVB_SOC_SEQ<<15)+(RST_SEQ1<<14)+(SOC_SEQ1<<13)+
(INT_ENA_SEQ1<<10)+(EVA_SOC_SEQ1<<8)+(EXT_SOC_SEQ1<<7)+
(RST_SEQ2<<6)+(SOC_SEQ2<<5)+(INT_ENA_SEQ1<<2)+
EVB_SOC_SEQ2);
/* Initialize ADC-sequencer */
PEDATDIR = 0xFF00; /* Clear Port E */
IMR=((INT6<<5)+(INT5<<4)+(INT4<<3)+
(INT3<<2)+(INT2<<1)+(INT1)); /* Interrupt Mask Register */
IFR=0xFFFF; /* Reset all core interrupts */
asm (" clrc INTM"); /* Enable all unmasked interrupts */
T1CON=T1CON+(T1CON_TENABLE<<6); /* enable GPT1 now */
while(1){
unsigned int i;
/* show_ADC() displays the latest result on LED's */
for(i=0;i<65000;i++)show_ADC(ADC0_result);
for(i=0;i<65000;i++)show_ADC(ADC1_result);
}
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