dil.c

TMS320F243 实验程序23 比较好用

/************************************************************************/
/* Testprogram for digital I/O on Port E and B							*/
/* running on TMS320LF2407 EVAL-Board, PLL is set to multiply by 2 		*/
/* external clock is 14.7456 MHz, PLL * 2 , CPU-Clock then 29.49 MHz	*/
/* date :  17.08.2000													*/
/************************************************************************/                                                                  
/* digital OUT on Port E0...E7 , digital IN on Port B0..B7		     	*/
/* 8 LED's connected to Port E0...E7 ; LED-on : 1  LED off : 0			*/
/* 8 Switches to GND connected to Port B0..B7							*/
/* LED's show the status of the Switches			 					*/ 
/* program-name :  DIL.c	/ project : DIL								*/											
/************************************************************************/

#include "regs2407.h"

/*************     SETUP for the MCRA - Register   **************/ 
#define MCRA15			0	/* 0 : IOPB7	1 : TCLKIN			*/
#define MCRA14			0	/* 0 : IOPB6	1 : TDIR			*/
#define MCRA13			0	/* 0 : IOPB5	1 : T2PWM			*/
#define MCRA12			0	/* 0 : IOPB4	1 : T1PWM			*/
#define MCRA11			0	/* 0 : IOPB3	1 : PWM6			*/
#define MCRA10			0	/* 0 : IOPB2	1 : PWM5			*/
#define MCRA9			0	/* 0 : IOPB1	1 : PWM4			*/
#define MCRA8			0   /* 0 : IOPB0	1 : PWM3			*/
#define MCRA7			0	/* 0 : IOPA7	1 : PWM2			*/
#define MCRA6			0	/* 0 : IOPA6	1 :	PWM1			*/
#define MCRA5			0	/* 0 : IOPA5	1 : CAP3			*/
#define MCRA4			0	/* 0 : IOPA4	1 :	CAP2/QEP2		*/
#define MCRA3			0	/* 0 : IOPA3	1 : CAP1/QEP1		*/
#define MCRA2			0	/* 0 : IOPA2	1 :	XINT1			*/
#define MCRA1			0	/* 0 : IOPA1	1 :	SCIRXD			*/
#define MCRA0			0	/* 0 : IOPA0	1 : SCITXD			*/
/****************************************************************/
/*************     SETUP for the MCRB - Register   **************/
#define MCRB9			0	/* 0 : IOPD1	1 : XINT2/EXTSOC	*/
#define MCRB8			1	/* 0 : CKLKOUT  1 : IOPD0			*/
#define MCRB7			0	/* 0 : IOPC7	1 : CANRX			*/
#define MCRB6			0	/* 0 : IOPC6	1 : CANTX			*/
#define MCRB5			0 	/* 0 : IOPC5	1 : SPISTE			*/
#define MCRB4			0	/* 0 : IOPC4	1 : SPICLK			*/
#define MCRB3			0	/* 0 : IOPC3	1 : SPISOMI			*/
#define MCRB2			0	/* 0 : IOPC2	1 : SPISIMO			*/
#define MCRB1			1	/* 0 : BIO		1 : IOPC1			*/
#define MCRB0			1	/* 0 : XF		1 : IOPC0			*/
/****************************************************************/
/*************     SETUP for the MCRC - Register   **************/ 
#define MCRC13			0	/* 0 : IOPF5	1 : TCLKIN2			*/
#define MCRC12			0	/* 0 : IOPF4	1 : TDIR2			*/
#define MCRC11			0	/* 0 : IOPF3	1 : T4PWM/T4CMP		*/
#define MCRC10			0	/* 0 : IOPF2	1 : T3PWM/T3CMP		*/
#define MCRC9			0	/* 0 : IOPF1	1 : CAP6			*/
#define MCRC8			0   /* 0 : IOPF0	1 : CAP5/QEP3		*/
#define MCRC7			0	/* 0 : IOPE7	1 : CAP4/QEP2		*/
#define MCRC6			0	/* 0 : IOPE6	1 :	PWM12			*/
#define MCRC5			0	/* 0 : IOPE5	1 : PWM11			*/
#define MCRC4			0	/* 0 : IOPE4	1 :	PWM10			*/
#define MCRC3			0	/* 0 : IOPE3	1 : PWM9			*/
#define MCRC2			0	/* 0 : IOPE2	1 :	PWM8			*/
#define MCRC1			0	/* 0 : IOPE1	1 :	PWM7			*/
#define MCRC0			0	/* 0 : IOPE0	1 : CLKOUT			*/
/****************************************************************/ 
/*************     SETUP for the WDCR - Register   **************/
#define WDDIS			1	/* 0 : Watchdog enabled 1: disabled */
#define WDCHK2			1	/* 0 : System reset   1: Normal OP	*/
#define WDCHK1			0	/* 0 : Normal Oper.	  1: sys reset	*/
#define WDCHK0			1	/* 0 : System reset   1: Normal OP	*/
#define WDSP			7	/* Watchdog prescaler 7 : div 64	*/
/****************************************************************/
/*************     SETUP for the SCSR1 - Register  **************/
#define CLKSRC			0	/* 0 : intern(20MHz)				*/
#define LPM				0	/* 0 : Low power mode 0 if idle		*/
#define CLK_PS			1	/* 001 : PLL multiply by 2			*/
#define ADC_CLKEN		0	/* 0 : No ADC-service in this test	*/
#define SCI_CLKEN		0   /* 0 : No SCI-service in this test  */
#define SPI_CLKEN		0	/* 0 : No SPI-servide in this test	*/
#define CAN_CLKEN		0	/* 0 : No CAN-service in this test	*/
#define EVB_CLKEN		0	/* 0 : No EVB-Service in this test	*/
#define EVA_CLKEN		0	/* 0 : No EVA-Service in this test	*/
#define ILLADR			1	/* 1 : Clear ILLADR during startup	*/
/****************************************************************/  
/*************     SETUP for the WSGR - Register   **************/
#define BVIS			0	/* 10-9 : 00 Bus visibility OFF		*/
#define ISWS			0	/* 8 -6 : 000 0 Waitstates for IO	*/
#define DSWS			0	/* 5 -3 : 000 0 Waitstates  data	*/
#define PSWS			0	/* 2 -0 : 000 0 Waitstaes code		*/
/****************************************************************/ 

unsigned int LED[8]={0xFF01,0xFF02,0xFF04,0xFF08,
					 0xFF10,0xFF20,0xFF40,0xFF80};
					 /* lookup table for Port E					*/ 
					 				       
void c_dummy1(void)
	{
	while(1);		/*Dummy ISR used to trap spurious interrupts*/
	}	   	 

void main(void)
{
 asm (" setc INTM");/*Disable all interrupts					*/
 asm (" clrc SXM");	/*Clear Sign Extension Mode bit				*/
 asm (" clrc OVM");	/*Reset Overflow Mode bit*/
 asm (" clrc CNF");	/*Configure block B0 to data mem.			*/

 WSGR=((BVIS<<9)+(ISWS<<6)+(DSWS<<3)+PSWS); 
 		 			/* setup external waitstates			    */
					
 WDCR=((WDDIS<<6)+(WDCHK2<<5)+(WDCHK1<<4)+(WDCHK0<<3)+WDSP);		
 					/* Initialize Watchdog-timer				*/
 
 SCSR1= ((CLKSRC<<14)+(LPM<<12)+(CLK_PS<<9)+(ADC_CLKEN<<7)+
 		   (SCI_CLKEN<<6)+(SPI_CLKEN<<5)+(CAN_CLKEN<<4)+
 		   (EVB_CLKEN<<3)+(EVA_CLKEN<<2)+ILLADR); 
 		   			/* Initialize SCSR 							*/ 
 
 MCRC = ((MCRC13<<13)+(MCRC12<<12)+(MCRC11<<11)+(MCRC10<<10)
 		 +(MCRC9<<9)+(MCRC8<<8)+(MCRC7<<7)+(MCRC6<<6)
 		 +(MCRC5<<5)+(MCRC4<<4)+(MCRC3<<3)+(MCRC2<<2)
 		 +(MCRC1<<1)+MCRC0);	
          			/* Initialize master control register C		*/  
 
 MCRB = ((MCRB9<<9)+(MCRB8<<8)+
 		  (MCRB7<<7)+(MCRB6<<6)+(MCRB5<<5)+(MCRB4<<4)+
 		  (MCRB3<<3)+(MCRB2<<2)+(MCRB1<<1)+MCRB0);
 		  			/* Initialize master control register B		*/
 		  
 MCRA = ((MCRA15<<15)+(MCRA14<<14)+(MCRA13<<13)+(MCRA12<<12)+
          (MCRA11<<11)+(MCRA10<<10)+(MCRA9<<9)+(MCRA8<<8)+
          (MCRA7<<7)+(MCRA6<<6)+(MCRA5<<5)+(MCRA4<<4)+
          (MCRA3<<3)+(MCRA2<<2)+(MCRA1<<1)+MCRA0);	
          			/* Initialize master control register A		*/  
 
 PBDATDIR = 0x0000;		/* use IOPB0..B7 as inputs				*/  
 
 PEDATDIR = 0xFF00;	   /* Clear Port E							*/
                          	
 
 while(1) PEDATDIR = 0xFF00 + (PBDATDIR & 0x00FF);
						/* endless loop
						   put input B0-B7 to output E0-E7		*/ 
						   
}