at24c32.c

TMS320F243 的实验程序 13

/************************************************************************/
/* Testprogram for an I2C-Bus on Port D0 ( SCL) and D1 (SDA)			*/
/* running on TMS320F243 EVA-Board, PLL is fixed to multiply by 4 		*/
/* external clock is 5MHz, internal then 20Mhz							*/
/* date :  07/14/2000 ,  (c) [e-mail]				*/
/************************************************************************/ 
/* Program to drive an external serial IIC-EEPROM ATMEL AT24Cxx         */
/* software delay loop								 					*/ 
/* program-name :  AT24C32.c	/ project : AT24C32						*/											
/* SCL = Port D-Bit 0													*/
/* SDA = Port D-Bit 1													*/
/* WP  = Port D-Bit 2													*/  
/* EEPROM A2=A1=A0 = 0													*/
/************************************************************************/

#include "regs243.h"

/*************     SETUP for the OCRA - Register   **************/ 
#define OCRA15			0	/* 0 : IOPB7	1 : TCLKIN			*/
#define OCRA14			0	/* 0 : IOPB6	1 : TDIR			*/
#define OCRA13			0	/* 0 : IOPB5	1 : T2PWM			*/
#define OCRA12			0	/* 0 : IOPB4	1 : T1PWM			*/
#define OCRA11			0	/* 0 : IOPB3	1 : PWM6			*/
#define OCRA10			0	/* 0 : IOPB2	1 : PWM5			*/
#define OCRA9			0	/* 0 : IOPB1	1 : PWM4			*/
#define OCRA8			0   /* 0 : IOPB0	1 : PWM3			*/
#define OCRA7			0	/* 0 : IOPA7	1 : PWM2			*/
#define OCRA6			0	/* 0 : IOPA6	1 :	PWM1			*/
#define OCRA5			0	/* 0 : IOPA5	1 : CAP3			*/
#define OCRA4			0	/* 0 : IOPA4	1 :	CAP2/QEP2		*/
#define OCRA3			0	/* 0 : IOPA3	1 : CAP1/QEP1		*/
#define OCRA2			0	/* 0 : IOPA2	1 :	XINT1			*/
#define OCRA1			0	/* 0 : IOPA1	1 :	SCIRXD			*/
#define OCRA0			0	/* 0 : IOPA0	1 : SCITXD			*/
/****************************************************************/
/*************     SETUP for the OCRB - Register   **************/
#define OCRB9			0	/* 0 : IOPD1	1 : XINT2/EXTSOC	*/
#define OCRB8			1	/* 0 : CKLKOUT  1 : IOPD0			*/
#define OCRB7			0	/* 0 : IOPC7	1 : CANRX			*/
#define OCRB6			0	/* 0 : IOPC6	1 : CANTX			*/
#define OCRB5			0 	/* 0 : IOPC5	1 : SPISTE			*/
#define OCRB4			0	/* 0 : IOPC4	1 : SPICLK			*/
#define OCRB3			0	/* 0 : IOPC3	1 : SPISOMI			*/
#define OCRB2			0	/* 0 : IOPC2	1 : SPISIMO			*/
#define OCRB1			1	/* 0 : BIO		1 : IOPC1			*/
#define OCRB0			1	/* 0 : XF		1 : IOPC0			*/
/****************************************************************/ 
/*************     SETUP for the WDCR - Register   **************/
#define WDDIS			1	/* 0 : Watchdog enabled 1: disabled */
#define WDCHK2			1	/* 0 : System reset   1: Normal OP	*/
#define WDCHK1			0	/* 0 : Normal Oper.	  1: sys reset	*/
#define WDCHK0			1	/* 0 : System reset   1: Normal OP	*/
#define WDSP			7	/* Watchdog prescaler 7 : div 64	*/
/****************************************************************/
/*************     SETUP for the SCSR - Register   **************/
#define CLKSRC			0	/* 0 : intern(20MHz)				*/
#define LPM				0	/* 0 : Low power mode 0 if idle		*/
/****************************************************************/  
/*************     SETUP for the WSGR - Register   **************/
#define BVIS			0	/* 10-9 : 00 Bus visibility OFF		*/
#define ISWS			0	/* 8 -6 : 000 0 Waitstates for IO	*/
#define DSWS			0	/* 5 -3 : 000 0 Waitstates  data	*/
#define PSWS			0	/* 2 -0 : 000 0 Waitstaes code		*/
/****************************************************************/
#define CLK_TIME 50
extern _out_wsgr();

void wait(unsigned int time)
/* delay for time */
{
	while(time--);	
}

void SET_SCL(void)
{
	PDDATDIR |= 1;
}

void CLR_SCL(void)
{
	PDDATDIR &=0xFFFE;
}

void SET_SDA(void)
{
	PDDATDIR |= 2;
}
	    
void CLR_SDA(void)
{
	PDDATDIR &=0xFFFD;
}


void output(unsigned int achtbit)
{
/*	writes 8 bit into EEPROM */ 
	int i,temp;
    PDDATDIR &=0xFFFE;  /* SCL =0 */
    for (i=7;i>=0;i--)
    {
    	temp = achtbit&(0x01<<i);
    	if (temp==0) CLR_SDA();	else SET_SDA();
    	wait(CLK_TIME);
    	SET_SCL();
    	wait(CLK_TIME);
    	CLR_SCL();
    	}
}
 	
                                
unsigned char input(void)
/* reads 8 Bit out of EEPROM */
{
	unsigned int i,puffer=0,temp=0;
	CLR_SCL();
	for(i=7;i>=0;i--)
		{
		wait(CLK_TIME);
		SET_SCL();
		wait(CLK_TIME);
		puffer = PDDATDIR & 0x0002; /*GET SDA */
		puffer = puffer >>1;
		temp  += puffer<<i;
		CLR_SCL();
		}
	return(temp);
}

void i2c_start(void)
{
	SET_SDA();
	wait(CLK_TIME);
	SET_SCL();
	wait(CLK_TIME);
	CLR_SDA();
	wait(CLK_TIME);
	CLR_SCL();
	wait(CLK_TIME);
}

void i2c_stop(void)
{
	CLR_SDA();
	CLR_SCL();
	wait(CLK_TIME);
	SET_SCL();
	wait(CLK_TIME);
	SET_SDA();
}
	
int get_ack(void)
/* returns the ACK-status from EEPROM */
{
	unsigned int temp;
	wait(CLK_TIME);
	CLR_SCL();
	SET_SDA();
	wait(CLK_TIME);
	SET_SCL();
	wait(CLK_TIME);
	temp= PDDATDIR & 0x0002;	/* get SDA */
	CLR_SCL();
	if (temp == 0 ) return(0); else return(-1);
}
 		                                
void write_byte(unsigned int chip, unsigned int address, unsigned int wrdata)
/* writes one byte into an EEPROM-address */
{
	unsigned int temp;
	i2c_start();
	chip = chip & 0x00FF;		/* only lower 8 bit */
	temp = (0x000A<<4) + (chip<<1) + 0;
	output(temp);
	get_ack();					/* no error handling ! */
	temp = address & 0xFF00;		/* address high byte		*/
	output(temp);          
	get_ack();
	temp = address & 0x00FF;	/* address low byte			*/
	output(temp);
	get_ack();
	temp = wrdata & 0x00FF;		/* data into EEPROM			*/
	output(temp);
	i2c_stop();
}

unsigned int read_byte(unsigned int chip,unsigned int address)
/* reads one byte out of EEPROM-address					*/
{
	unsigned int temp;
	i2c_start();
	temp = (0x000A<<4) + (chip<<1) +0;
	output(temp);
	get_ack();
	temp = address & 0xFF00;
	output(temp);
	get_ack();
	temp = address & 0x00FF;
	output(temp);
	get_ack();
	i2c_start();
	temp = (0x000A<<4) + (chip<<1) + 1 ;
	output(temp);
	get_ack();
	temp = input();
	i2c_stop();
	return(temp);
}

void polling(unsigned int chip)
/* waits until internal write into EEPROM has finished			*/
{
	unsigned int temp;
	wait(CLK_TIME);
	while(1)
		{
		i2c_start();
		temp = ( 0x000A<<4) + (chip<<1) + 0;
		output(temp);
		if(get_ack()==0) { i2c_stop; break;}
		i2c_stop();
		}
}

	
void c_dummy1(void)
{
	while(1);		/*Dummy ISR used to trap spurious interrupts*/
}

void main(void)
{
 unsigned int addr = 0x100;
 unsigned int daten = 0xaa; 
 unsigned int result;
 
 asm (" setc INTM");/*Disable all interrupts					*/
 asm (" clrc SXM");	/*Clear Sign Extension Mode bit				*/
 asm (" clrc OVM");	/*Reset Overflow Mode bit*/
 asm (" clrc CNF");	/*Configure block B0 to data mem.			*/

 out_wsgr((BVIS<<9)+(ISWS<<6)+(DSWS<<3)+PSWS); 
 		 			/* external Function for access  WSGR	    */
					
 WDCR=((WDDIS<<6)+(WDCHK2<<5)+(WDCHK1<<4)+(WDCHK0<<3)+WDSP);		
 					/* Initialize Watchdog-timer				*/
 
 SCSR = ((CLKSRC<<15)+(LPM<<13)); /* Initialize SCSR 			*/ 
 					   	
 OCRB = ((OCRB9<<9)+(OCRB8<<8)+
 		  (OCRB7<<7)+(OCRB6<<6)+(OCRB5<<5)+(OCRB4<<4)+
 		  (OCRB3<<3)+(OCRB2<<2)+(OCRB1<<1)+OCRB0);
 		  			/* Initialize output control register B		*/
 		  
  
 OCRA = ((OCRA15<<15)+(OCRA14<<14)+(OCRA13<<13)+(OCRA12<<12)+
          (OCRA11<<11)+(OCRA10<<10)+(OCRA9<<9)+(OCRA8<<8)+
          (OCRA7<<7)+(OCRA6<<6)+(OCRA5<<5)+(OCRA4<<4)+
          (OCRA3<<3)+(OCRA2<<2)+(OCRA1<<1)+OCRA0);	
          			/* Initialize output control register A		*/
                    	
 while(1){
 		PDDATDIR = 0xFF00;   /* SCI and SDA cleared to 0 */
		PDDATDIR &=0xFFFB;	 /* WP = 0 , no write protect */
		write_byte(0,addr,daten);
		polling(0);
		result=read_byte(0,addr);
		while(1);			/*  stop execution here			*/		
		
 	}	
 }