📄 skyeye_mach_at91.c
字号:
break;
case 0x7: // THR
{
char c = data;
write (skyeye_config.uart.fd_out, &c, 1);
}
//printf("%c", data); fflush(stdout);
break;
case 0x8: // BRGR
case 0xa: // TTGR
case 0xb: // RES1
DBG_PRINT ("uart_write(%s=0x%x) = 0x%08x\n",
uart_reg[(addr & 0xfff) >> 2], addr, data);
break;
case 0xd: // RCR
rcr = data;
if (rcr == 0)
io.sysflg &= ~URXFE;
else
io.sysflg |= URXFE;
break;
case 0xc: // RPR
DBG_PRINT ("uart_write(%s=0x%x) = 0x%08x\n",
uart_reg[(addr & 0xfff) >> 2], addr, data);
rpr = data;
break;
case 0xe: // TPR
tx_buf = data;
break;
case 0xf: // TCR
for (; tx_buf && data > 0; data--)
{
char c = mem_read_char (state, tx_buf++);
write (skyeye_config.uart.fd_out, &c, 1);
//printf("%c", mem_read_char(state, tx_buf++));
//fflush(stdout);
}
tx_buf = 0;
break;
}
}
ARMword
at91_io_read_byte (ARMul_State * state, ARMword addr)
{
return 0;
}
ARMword
at91_io_read_halfword (ARMul_State * state, ARMword addr)
{
return 0;
}
ARMword
at91_io_read_word (ARMul_State * state, ARMword addr)
{
ARMword data = -1;
int i;
ARMword ts_addr;
ts_addr = addr & ~3; // 1 word==4 byte
if (ts_addr >= io.ts_addr_begin && ts_addr <= io.ts_addr_end)
{
data = io.ts_buffer[(ts_addr - io.ts_addr_begin) / 4];
return data;
}
switch (addr)
{
case 0xfffff100: /* IVR */
data = io.ipr;
DBG_PRINT ("IVR irqs=%x ", data);
for (i = 0; i < 32; i++)
if (data & (1 << i))
break;
if (i < 32)
{
data = i;
io.ipr &= ~(1 << data);
at91_update_int (state);
}
else
data = 0;
io.ivr = data;
//current_ivr = data;
DBG_PRINT ("read IVR=%d\n", data);
break;
case 0xfffff108: /* interrupt status register */
// data = current_ivr;
data = io.ivr;
break;
case 0xfffff110: /* IMR */
data = io.imr;
break;
case 0xfffff114: /* CORE interrupt status register */
data = io.cisr;
data = io.imr;
break;
case 0xfffff120: /* IECR */
data = io.iecr;
data = io.imr;
break;
case 0xfffff124: /* IDCR */
break;
case 0xfff00000: /* CPU ID */
data = 0x2078aa0;
data = 0x14000040;
break;
case 0xfffe00c0: /* TIMER 1 BCR */
DBG_PRINT ("T1-BCR io_read_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe00c4: /* TIMER 1 BMR */
DBG_PRINT ("T1-BMR io_read_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0040: /* TIMER 1 CCR */
DBG_PRINT ("T1-CCR io_read_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0044: /* TIMER 1 CMR */
DBG_PRINT ("T1-CMR io_read_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0068: /* TIMER 1 IDR */
DBG_PRINT ("T1-IDR io_read_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0050: /* TIMER 1 CV */
DBG_PRINT ("T1-CV io_read_word(0x%08x) = 0x%08x\n", addr, data);
data = io.tcd[0];
break;
case 0xfffe005c: /* TIMER 1 RC */
DBG_PRINT ("T1-RC io_read_word(0x%08x) = 0x%08x\n", addr, data);
data = io.tcd[0];
break;
case 0xfffe0060: /* TIMER 1 SR */
DBG_PRINT ("T1-SR io_read_word(0x%08x) = 0x%08x\n", addr, data);
//io.ipr &= ~(1<<IRQ_TC1);
break;
case 0xfffe0064: /* TIMER 1 IER */
DBG_PRINT ("T1-IER io_read_word(0x%08x) = 0x%08x\n", addr, data);
break;
default:
if ((addr & 0xffffff00) == 0xfffff000)
break;
if ((addr & 0xfffff000) == 0xfffd0000)
{
data = uart_read (state, addr);
break;
}
if ((addr & 0xfffff000) == 0xfffcc000)
{
data = uart_read (state, addr);
break;
}
//fprintf (stderr,
// "NumInstr %llu, io_read_word unknown addr(0x%08x) = 0x%08x\n",
// state->NumInstrs, addr, data);
//SKYEYE_OUTREGS (stderr);
//ARMul_Debug(state, 0, 0);
break;
}
return data;
}
void
at91_io_write_byte (ARMul_State * state, ARMword addr, ARMword data)
{
return;
}
void
at91_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data)
{
return;
}
void
at91_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
/*
* The Atmel system registers
*/
switch (addr)
{
case 0xfffff108: /* ISR */
//DBG_PRINT("write ISR=0x%x\n", data);
//io.isr = data;
break;
case 0xfffff110: /* IMR */
//io.imr = data;
break;
case 0xfffff114: /* CORE interrupt status register */
//io.cisr = data;
DBG_PRINT ("write CISR=0x%x\n", data);
break;
case 0xfffff120: /* IECR */
DBG_PRINT ("IECR=0x%x\n", data);
io.iecr = data;
io.imr |= data;
break;
case 0xfffff124: /* IDCR */
DBG_PRINT ("IDCR=0x%x\n", data);
io.idcr = data;
io.imr &= ~data;
break;
case 0xfffff128: /* CLEAR interrupts */
DBG_PRINT ("ICCR=0x%x\n", data);
io.iccr = data;
io.ipr &= ~data;
break;
case 0xfffff130: /* EOI */
DBG_PRINT (stderr, "EOI=0x%x\n", data);
io.eoicr = data;
io.ipr &= ~data;
at91_update_int (state);
break;
case 0xfff00000: /* CPU ID */
break;
case 0xfffe00c0: /* TIMER 1 BCR */
DBG_PRINT ("T1-BCR io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe00c4: /* TIMER 1 BMR */
DBG_PRINT ("T1-BMR io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0040: /* TIMER 1 CCR */
DBG_PRINT ("T1-CCR io_write_word(0x%08x) = 0x%08x\n", addr, data);
if (data & 0x2)
{
io.syscon &= ~TC1M;
}
else
{
io.syscon |= TC1M;
}
break;
case 0xfffe0044: /* TIMER 1 CMR */
DBG_PRINT ("T1-CMR io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0068: /* TIMER 1 IDR */
DBG_PRINT ("T1-IDR io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0050: /* TIMER 1 CV */
DBG_PRINT ("T1-CV io_write_word(0x%08x) = 0x%08x\n", addr, data);
io.tcd[0] = io.tcd_reload[0] = data & 0xffff;
break;
case 0xfffe005c: /* TIMER 1 RC */
DBG_PRINT ("T1-RC io_write_word(0x%08x) = 0x%08x\n", addr, data);
io.tcd[0] = io.tcd_reload[0] = data & 0xffff;
break;
case 0xfffe0060: /* TIMER 1 SR */
DBG_PRINT ("T1-SR io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
case 0xfffe0064: /* TIMER 1 IER */
DBG_PRINT ("T1-IER io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
default:
if ((addr & 0xfffff000) == 0xfffd0000)
{
uart_write (state, addr, data);
break;
}
if ((addr & 0xfffff000) == 0xfffcc000)
{
uart_write (state, addr, data);
break;
}
if ((addr & 0xffffff00) == 0xfffff000)
break;
if ((addr & 0xffff0000) == 0xffff0000)
{
DBG_PRINT ("io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
}
//DBG_PRINT("io_write_word(0x%08x) = 0x%08x\n", addr, data);
//fprintf (stderr,
// "NumInstr %llu,io_write_word unknown addr(0x%08x) = 0x%08x\n",
// state->NumInstrs, addr, data);
//SKYEYE_OUTREGS (stderr);
//ARMul_Debug(state, 0, 0);
break;
}
}
void
at91_mach_init (ARMul_State * state, machine_config_t * this_mach)
{
//chy 2003-08-19, setprocessor
ARMul_SelectProcessor (state, ARM_v4_Prop);
//chy 2004-05-09, set lateabtSig
state->lateabtSig = HIGH;
this_mach->mach_io_do_cycle = at91_io_do_cycle;
this_mach->mach_io_reset = at91_io_reset;
this_mach->mach_io_read_byte = at91_io_read_byte;
this_mach->mach_io_write_byte = at91_io_write_byte;
this_mach->mach_io_read_halfword = at91_io_read_halfword;
this_mach->mach_io_write_halfword = at91_io_write_halfword;
this_mach->mach_io_read_word = at91_io_read_word;
this_mach->mach_io_write_word = at91_io_write_word;
this_mach->mach_update_int = at91_update_int;
this_mach->mach_set_intr = at91_set_intr;
this_mach->mach_pending_intr = at91_pending_intr;
this_mach->mach_update_intr = at91_update_intr;
this_mach->mach_mem_read_byte = at91_mem_read_byte;
this_mach->mach_mem_write_byte = at91_mem_write_byte;
this_mach->state = (void *) state;
}
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