entries.extra

一个嵌入式RISC CPU 的Verilog 设计源码

/ACC.V////
/ALU.V////
/CONTROL.V////
/IR.V////
/MEM.V////
/MUX12.V////
/MUX16.V////
/PC.V////
/bus_arbiter.v////
/cmd_ack.v////
/cmd_decoder.v////
/cmd_detector.v////
/cmd_generator.v////
/cmd_internal_reg.v////
/command_if.v////
/data_cache_way0.v////
/data_cache_way1.v////
/data_cache_way2.v////
/data_cache_way3.v////
/data_in_reg.v////
/data_port.v////
/dma_cntrl.v////
/dma_fifo.v////
/dma_internal_reg.v////
/flash_ctrl.v////
/fsm.v////
/instruction_cache_way0.v////
/instruction_cache_way1.v////
/instruction_cache_way2.v////
/instruction_cache_way3.v////
/k9f1g08u0m.v////
/lru_data_cache.v////
/lru_instruction_cache.v////
/oe_generator.v////
/parameter.v////
/ras_cas_delay.v////
/ref_ack.v////
/ref_timer.v////
/risc.v////
/sdram.v////
/sdram_cntrl.v////
/sdram_mux.v////
/sdram_port.v////
/sdramctrl_rtl.v////
/soc.v////
/timer.v////
/uart.v////