entries

一个嵌入式RISC CPU 的Verilog 设计源码

/ACC.V/1.1/Wed Jun  5 22:38:44 2002//
/ALU.V/1.1/Wed Jun  5 22:38:44 2002//
/CONTROL.V/1.1/Wed Jun  5 22:38:44 2002//
/IR.V/1.1/Wed Jun  5 22:38:44 2002//
/MEM.V/1.1/Wed Jun  5 22:38:44 2002//
/MUX12.V/1.1/Wed Jun  5 22:38:44 2002//
/MUX16.V/1.1/Wed Jun  5 22:38:44 2002//
/PC.V/1.1/Wed Jun  5 22:38:44 2002//
/bus_arbiter.v/1.1/Wed Jun  5 22:38:44 2002//
/cmd_ack.v/1.1/Wed Jun  5 22:38:44 2002//
/cmd_decoder.v/1.1/Wed Jun  5 22:38:44 2002//
/cmd_detector.v/1.1/Wed Jun  5 22:38:44 2002//
/cmd_generator.v/1.1/Wed Jun  5 22:38:44 2002//
/cmd_internal_reg.v/1.1/Wed Jun  5 22:38:44 2002//
/command_if.v/1.1/Wed Jun  5 22:38:44 2002//
/data_cache_way0.v/1.1/Wed Jun  5 22:38:44 2002//
/data_cache_way1.v/1.1/Wed Jun  5 22:38:44 2002//
/data_cache_way2.v/1.1/Wed Jun  5 22:38:44 2002//
/data_cache_way3.v/1.1/Wed Jun  5 22:38:44 2002//
/data_in_reg.v/1.1/Wed Jun  5 22:38:44 2002//
/data_port.v/1.1/Wed Jun  5 22:38:44 2002//
/dma_cntrl.v/1.1/Wed Jun  5 22:38:44 2002//
/dma_fifo.v/1.1/Wed Jun  5 22:38:44 2002//
/dma_internal_reg.v/1.1/Wed Jun  5 22:38:44 2002//
/flash_ctrl.v/1.1/Wed Jun  5 22:38:44 2002//
/fsm.v/1.1/Wed Jun  5 22:38:44 2002//
/instruction_cache_way0.v/1.1/Wed Jun  5 22:38:44 2002//
/instruction_cache_way1.v/1.1/Wed Jun  5 22:38:44 2002//
/instruction_cache_way2.v/1.1/Wed Jun  5 22:38:44 2002//
/instruction_cache_way3.v/1.1/Wed Jun  5 22:38:44 2002//
/k9f1g08u0m.v/1.1/Wed Jun  5 22:38:44 2002//
/lru_data_cache.v/1.1/Wed Jun  5 22:38:44 2002//
/lru_instruction_cache.v/1.1/Wed Jun  5 22:38:44 2002//
/oe_generator.v/1.1/Wed Jun  5 22:38:44 2002//
/parameter.v/1.1/Wed Jun  5 22:38:44 2002//
/ras_cas_delay.v/1.1/Wed Jun  5 22:38:44 2002//
/ref_ack.v/1.1/Wed Jun  5 22:38:44 2002//
/ref_timer.v/1.1/Wed Jun  5 22:38:44 2002//
/risc.v/1.1/Wed Jun  5 22:38:44 2002//
/sdram.v/1.1/Wed Jun  5 22:38:44 2002//
/sdram_cntrl.v/1.1/Wed Jun  5 22:38:44 2002//
/sdram_mux.v/1.1/Wed Jun  5 22:38:44 2002//
/sdram_port.v/1.1/Wed Jun  5 22:38:44 2002//
/sdramctrl_rtl.v/1.1/Wed Jun  5 22:38:44 2002//
/soc.v/1.1/Wed Jun  5 22:38:44 2002//
/timer.v/1.1/Wed Jun  5 22:38:44 2002//
/uart.v/1.1/Wed Jun  5 22:38:44 2002//
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