gpiodrv.h

56f8300E系列dsp的BOOTloader

/*****************************************************************************
*
* giopdrv.h - header file for the general purpose IO driver.
*
*  The DSP56838 processor has following general purpose I/O ports:
*     Port A which is located in memory space from 0xFFF2E0
*     Port B which is located in memory space from 0xFFF300
*     Port C which is located in memory space from 0xFFF310
*     Port D which is located in memory space from 0xFFF320
*     Port E which is located in memory space from 0xFFF330
*  
*  Each Port is comprised of nine registers. GIOP registers are placed on 
*  the chip in groups of eight bits. They are as follows:
*
*  1) GPIO_Pull-Up Enable Register (PUR): This is a read/write register.
*     The PUR is for pull-up enabling, PUR set to one, and disabling, PUR
*     set to 0.
*
*  2) Data Register (DR): This is a read/write register.  The DR is for 
*     holding data that comes from the PAD or the IP Bus.
*
*  3) Data Direction Register (DDR):  This is a read/write register.  This
*     register configures a particular pin as either an input, set to one,
*     or an output, set to zero.    
* 	 
*  4) Peripheral Enable Register (PER):  This is a read/write register.  
*     This register determines the GPIOs configuration.  Setting a bit to 
*     one makes the peripheral master the GPIO pin.  When a bit is set to 
*     zero the Data Direction Register determines the direction of data 
*     flow through the pin.
*  
*  5) Interrupt Assert Register (IAR):  This is a read/write register.  
*     The IAR register is used only in software testing.  When the IAR is 
*     a one an interrupt is asserted and can be cleared by writing zeros 
*     into the IAR.
*
*  6) Interrupt Enable Register (IENR):  This is a read/write register.  It
*     enables or disables the edge detection for any incoming interrupt from
*     the PAD.  This register is set to one for interrupt detection.
*
*  7) Interrupt Polarity Register (IPOL): This read/write register. It is 
*     used for polarity detection caused by any external interrupts. When
*     this register is set to one, the interrupt at the PAD is active low
*     and when this register is set to zero, the interrupt seen at the PAD
*     is active high. This is true only when the IENR is set to one. There
*     is no any effect on the interrupt if the IENR is set to zero.
*
*  8) Interrupt Pending Register (IPR): This read only register is used to
*     record any incoming interrupts. The user can read this register to 
*     determine which pin has caused the interrupt. This register can be 
*     cleared by writing zeros into the IAR register if the interrupt is 
*     caused by software. For an external interrupts, the IPR is cleared 
*     by writing ones into the IESR (Interrupt Edge Sensitive Register).
*
*  9) Interrupt Edge Sensitive Register (IESR): When an edge is detected by
*     the edge detector circuit, and the IENR is set to one, the IESR 
*     records the interrupt. This register is read/write, however, the only
*     time the user can write into this register is to clear the IPR register
*     only. The user can only write ones into this register to clear the IPR.
*****************************************************************************/
#ifndef GIOPDRV_H
#define GIOPDRV_H

#include "port.h"
#include "bsp.h"
#include "gpio.h"
#include "arch.h"

#ifdef __cplusplus
extern "C" {
#endif

#define GPIO_PORTA_SIZE     8
#define GPIO_PORTB_SIZE     8
#define GPIO_PORTC_SIZE     4
#define GPIO_PORTD_SIZE     8
#define GPIO_PORTE_SIZE     8

typedef void (*tpGpioCallback)( unsigned short );

typedef struct
{
   io_sInterface *      drvInterface;
   unsigned short       Base;
   unsigned short       Mask;
} sGpioDevice;

typedef const struct 
{
	ssize_t  (*pRead)(handle_t hndl, void *buf, size_t);
	ssize_t  (*pWrite)(handle_t hndl, const void *buf, size_t len);
	int      (*pClose)(handle_t hndl);
	unsigned short  (*pIoctl[17])(handle_t hndl, unsigned long params );
} io_sGPIOInterface;

#if defined(BSP_DEVICE_NAME_GPIO_A)
#define GPIO_A_BASE_ADDRESS        ((unsigned short)((const struct arch_IO *)&ArchIO.PortA))
#endif /* defined(BSP_DEVICE_NAME_GPIO_A) */
#if defined(BSP_DEVICE_NAME_GPIO_B)
#define GPIO_B_BASE_ADDRESS        ((unsigned short)((const struct arch_IO *)&ArchIO.PortB))
#endif /* defined(BSP_DEVICE_NAME_GPIO_B) */
#if defined(BSP_DEVICE_NAME_GPIO_C)
#define GPIO_C_BASE_ADDRESS        ((unsigned short)((const struct arch_IO *)&ArchIO.PortC))
#endif /* defined(BSP_DEVICE_NAME_GPIO_C) */
#if defined(BSP_DEVICE_NAME_GPIO_D)
#define GPIO_D_BASE_ADDRESS        ((unsigned short)((const struct arch_IO *)&ArchIO.PortD))
#endif /* defined(BSP_DEVICE_NAME_GPIO_D) */
#if defined(BSP_DEVICE_NAME_GPIO_E)
#define GPIO_E_BASE_ADDRESS        ((unsigned short)((const struct arch_IO *)&ArchIO.PortE))
#endif /* defined(BSP_DEVICE_NAME_GPIO_E) */

/*****************************************************************************/
/*                         API Function prototypes                           */
/*****************************************************************************/

EXPORT handle_t gpioOpen(const char * pName, int OFlags, ...);  
EXPORT int gpioClose(handle_t hndl); 
EXPORT ssize_t gpioRead(handle_t hndl, void * pBuffer, size_t NBytes);
EXPORT ssize_t gpioWrite(handle_t hndl, const void * pBuffer, size_t NBytes);
EXPORT handle_t gpioOpen(const char * pName, int OFlags, ...);  

EXPORT int gpiopinClose(handle_t hndl); 
EXPORT ssize_t gpiopinRead(handle_t hndl, void * pBuffer, size_t NBytes);
EXPORT ssize_t gpiopinWrite(handle_t hndl, const void * pBuffer, size_t NBytes);

//#define gpioClose(hndl) (0)
int gpioCreate(void);
//#define gpioCreate(name) 


/*****************************************************************************
* Prototypes - See source file for functional descriptions
******************************************************************************/

unsigned short gpioIoctlGPIO_SET( handle_t hndl, unsigned long params);
unsigned short gpioIoctlGPIO_CLEAR( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_TOGGLE( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_DISABLE_PULLUP( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_ENABLE_PULLUP( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_SETAS_INPUT( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_SETAS_OUTPUT( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_SETAS_GPIO( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_SETAS_PERIPHERAL( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_INTERRUPT_ASSERT_DISABLE( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_INTERRUPT_ASSERT_ENABLE( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_INTERRUPT_DISABLE( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_INTERRUPT_ENABLE( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_HIGH( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_LOW( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_CLEAR_INTERRUPT_PEND_REGISTER( handle_t hndl, unsigned long params );
unsigned short gpioIoctlGPIO_READ( handle_t hndl, unsigned long params );

unsigned short gpiopinIoctlGPIO_SET( handle_t hndl, unsigned long params);
unsigned short gpiopinIoctlGPIO_CLEAR( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_TOGGLE( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_DISABLE_PULLUP( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_ENABLE_PULLUP( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_SETAS_INPUT( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_SETAS_OUTPUT( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_SETAS_GPIO( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_SETAS_PERIPHERAL( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_INTERRUPT_ASSERT_DISABLE( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_INTERRUPT_ASSERT_ENABLE( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_INTERRUPT_DISABLE( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_INTERRUPT_ENABLE( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_HIGH( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_LOW( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_CLEAR_INTERRUPT_PEND_REGISTER( handle_t hndl, unsigned long params );
unsigned short gpiopinIoctlGPIO_READ( handle_t hndl, unsigned long params );

void gpioPinInit( handle_t hndl, int OFlags );

/* Redefine ioctl calls to map to standard driver */
#define gpioIoctl(FD,Cmd,pParams) gpioIoctl##Cmd(FD, pParams)
#define gpiopinIoctl(FD,Cmd,pParams) gpiopinIoctl##Cmd(FD, pParams)

#if defined(BSP_DEVICE_NAME_GPIO_A)
extern sGpioDevice pinPortAMap[];
#endif /* defined(BSP_DEVICE_NAME_GPIO_A) */

#if defined(BSP_DEVICE_NAME_GPIO_B)
extern sGpioDevice pinPortBMap[];
#endif /* defined(BSP_DEVICE_NAME_GPIO_B) */

#if defined(BSP_DEVICE_NAME_GPIO_C)
extern sGpioDevice pinPortCMap[];
#endif /* defined(BSP_DEVICE_NAME_GPIO_C) */

#if defined(BSP_DEVICE_NAME_GPIO_D)
extern sGpioDevice pinPortDMap[];
#endif /* defined(BSP_DEVICE_NAME_GPIO_D) */

#if defined(BSP_DEVICE_NAME_GPIO_E)
extern sGpioDevice pinPortEMap[];
#endif /* defined(BSP_DEVICE_NAME_GPIO_E) */


/* registry offsets */
#define GPIO_PULLUP_REG_OFFSET            0x00
#define GPIO_DATA_REG_OFFSET              0x01
#define GPIO_DATA_DIRECTION_REG_OFFSET    0x02
#define GPIO_PERIPHERAL_ENABLE_REG_OFFSET 0x03
#define GPIO_INT_ASSERT_REG_OFFSET        0x04
#define GPIO_INT_ENABLE_REG_OFFSET        0x05
#define GPIO_INT_POLARITY_REG_OFFSET      0x06
#define GPIO_INT_PENDING_REG_OFFSET       0x07
#define GPIO_INT_EDGE_SENS_REG_OFFSET     0x08

/* values for OFlags */
#if defined( O_RDONLY )
    #define O_SETAS_INPUT                   O_RDONLY
#else
    #define O_SETAS_INPUT                   0x0001
#endif
#if defined( O_WRONLY )
    #define O_SETAS_OUTPUT                  O_WRONLY
#else
    #define O_SETAS_OUTPUT                  0x0002
#endif


#ifdef __cplusplus
}
#endif

#endif