scidrv.h

56f8300E系列dsp的BOOTloader

/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
* Description:      Header file for the DSP56838 SCI device driver 
*
* Notes:  
*
******************************************************************************/

#ifndef __SCIDRV_H
#define __SCIDRV_H

#include "port.h"
#include "arch.h"
#include "sci.h"

#ifdef __cplusplus
extern "C" {
#endif


/*****************************************************************************/
/*                         Data structures                           		*/
/*****************************************************************************/

/* QUEUE	*/

struct sQueue
{
	volatile unsigned int 	begin;			/* iterator for begin of transmitting sequence 	*/
	volatile unsigned int 	end;			/* iterator for end of transmitting sequence 	*/
	volatile unsigned int	mask;			/* mask for round buffer /size - 1/				*/
	volatile unsigned int 	bufferOffset;	/* pointer to buffer 							*/
			 unsigned long  reserved;
};

/* Enumerators to access structure's fields */
enum QueueEnum
{
		sQueue_offset_begin			= (int)&((struct sQueue*)0)->begin,
		sQueue_offset_end			= (int)&((struct sQueue*)0)->end,
		sQueue_offset_mask			= (int)&((struct sQueue*)0)->mask,
		sQueue_offset_bufferOffset	= (int)&((struct sQueue*)0)->bufferOffset
};

struct sSciDevice
{
   io_sInterface *     	drvInterface;
   arch_sSCI*      	    Base;
   unsigned int        	Mask;
   struct 	sQueue   	qReceive; 
   struct 	sQueue   	qSend;
} ;

/*
	Enumerators for access to structure's fields
*/
enum SCIDeviceEnum
	{
		sSciDevice_offset_Base 		= (int)&((struct sSciDevice*)0)->Base,
		sSciDevice_offset_Mask 		= (int)&((struct sSciDevice*)0)->Mask,
		sSciDevice_offset_qReceive	= (int)&((struct sSciDevice*)0)->qReceive,
		sSciDevice_offset_qSend 	= (int)&((struct sSciDevice*)0)->qSend
	};

/*
	Virtual IO interface 
*/	
struct io_sSCIInterface
{
	ssize_t  	(*pRead)(handle_t hndl, void *buf, size_t);
	ssize_t  	(*pWrite)(handle_t hndl, const void *buf, size_t len);
	int      	(*pClose)(handle_t hndl);
	unsigned int(*pIoctl[11])(handle_t hndl, unsigned long params );	
} ;

/*****************************************************************************
* Ioctl Prototypes - See source file for functional descriptions
******************************************************************************/
unsigned int sciIoctlSCI_DEVICE_RESET( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_GET_STATUS( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_DEVICE_OFF( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_DEVICE_ON( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_CMD_SEND_BREAK( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_CMD_WAIT( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_CMD_WAKEUP( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_GET_COUNT_READ( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_GET_COUNT_WRITE( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_GET_READ_BUFFER_SIZE( handle_t hndl, unsigned long params );
unsigned int sciIoctlSCI_GET_WRITE_BUFFER_SIZE( handle_t hndl, unsigned long params );

/*****************************************************************************
*								Interrupt handlers
*****************************************************************************/

EXPORT void sciTransmitterISR(volatile register arch_sSCI * pArch , struct sSciDevice * pContext, tSciCallBackPtr callback);
EXPORT void sciReceiverISR(volatile register arch_sSCI * pArch , struct sSciDevice * pContext, tSciCallBackPtr callback);

/* Device descriptors */
extern struct sSciDevice Sci0DeviceContext;
extern struct sSciDevice Sci1DeviceContext;

#define BSP_LOW_DEVICE_NAME_SCI_0 ((const char *)&Sci0DeviceContext)
#define BSP_LOW_DEVICE_NAME_SCI_1 ((const char *)&Sci1DeviceContext)


handle_t sciPreOpen( const char * pName, struct io_sDevice* pDev, int OFlags , ... );



/*****************************************************************************
*							Macro Definitions
*****************************************************************************/

#define noSciOpen			NULL
#define noSciClose			NULL
#define noSciBlockRead		NULL
#define noSciBlockWrite		NULL
#define noSciNonBlockRead	NULL
#define noSciNonBlockWrite	NULL
#define noSciIoctl			NULL

// #define SCI_REG(base, offset)    ((volatile unsigned short *)(((int*)base) + (offset)))   

/* SCI register offsets description */
#define SCI_SCIBR             0x0000u
#define SCI_SCICR             0x0001u
#define SCI_SCISR             0x0003u
#define SCI_SCIDR             0x0004u

/* GPIO register offsets */
#define SCI_GPIO_DR           0x0001u
#define SCI_GPIO_DDR          0x0002u
#define SCI_GPIO_PER          0x0003u


/* SCI baud rate */
#define SCI_SCIBR_BAUD_MASK   0x1fffu

/* SCICR mode select bits */
#define SCI_SCICR_LOOP        0x8000u
#define SCI_SCICR_SWAI        0x4000u
#define SCI_SCICR_RSRC        0x2000u
#define SCI_SCICR_M           0x1000u
#define SCI_SCICR_WAKE        0x0800u
#define SCI_SCICR_POL         0x0400u
#define SCI_SCICR_PE          0x0200u
#define SCI_SCICR_PT          0x0100u
#define SCI_SCICR_TEIE        0x0080u
#define SCI_SCICR_TIIE        0x0040u
#define SCI_SCICR_RIE         0x0020u
#define SCI_SCICR_REIE        0x0010u
#define SCI_SCICR_TE          0x0008u
#define SCI_SCICR_RE          0x0004u
#define SCI_SCICR_RWU         0x0002u
#define SCI_SCICR_SBK         0x0001u

#define SCI_SCICR_USER_MASK ( SCI_SCICR_LOOP | \
                              SCI_SCICR_SWAI | \
                              SCI_SCICR_RSRC | \
                              SCI_SCICR_M    | \
                              SCI_SCICR_WAKE | \
                              SCI_SCICR_POL  | \
                              SCI_SCICR_PE   | \
                              SCI_SCICR_PT   ) 

/* SCI Status Registers bits */
#define SCI_SCISR_TDRE        0x8000u
#define SCI_SCISR_TIDLE       0x4000u
#define SCI_SCISR_RDRF        0x2000u
#define SCI_SCISR_RIDLE       0x1000u
#define SCI_SCISR_OR          0x0800u
#define SCI_SCISR_NF          0x0400u
#define SCI_SCISR_FE          0x0200u
#define SCI_SCISR_PF          0x0100u
#define SCI_SCISR_RAF         0x0001u

/* SCI Data Register  data mask */
#define SCI_SCIDR_7BIT_MASK   0x007fu
#define SCI_SCIDR_8BIT_MASK   0x00ffu
#define SCI_SCIDR_9BIT_MASK   0x01ffu
#define SCI_SCIDR_MSB         0x0100u

#define SCI0_BASE_ADDRESS        &ArchIO.Sci0
#define SCI0_GPIO_BASE_ADDRESS   &ArchIO.PortE
#define SCI0_GPIO_MASK           0x0003u    /* TXD0 (GPIOE0), RXD0 (GPIOE1) */

#define SCI1_BASE_ADDRESS        &ArchIO.Sci1
#define SCI1_GPIO_BASE_ADDRESS   &ArchIO.PortD
#define SCI1_GPIO_MASK           0x00C0u    /* TXD1 (GPIOD6), RXD1 (GPIOD7) */

#ifdef __cplusplus
}
#endif

#endif