📄 config.h
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#if ( CAN_SPEED == 250000 )
#define CAN_PROP_SEGMENT 7
#define CAN_PHASE_SEGMENT1 4 /* = 11 */
#define CAN_PHASE_SEGMENT2 4
#define CAN_DIVIDER 1
#define CAN_MIN_FREQUENCY 4
#endif /* CAN_SPEED == 250000 */
#if ( CAN_SPEED == 125000 )
#define CAN_PROP_SEGMENT 7
#define CAN_PHASE_SEGMENT1 4 /* = 11 */
#define CAN_PHASE_SEGMENT2 4
#define CAN_DIVIDER 2
#define CAN_MIN_FREQUENCY 4
#endif /* CAN_SPEED == 125000 */
#if ( CAN_SPEED == 100000 )
#define CAN_PROP_SEGMENT 7
#define CAN_PHASE_SEGMENT1 6 /* = 13 */
#define CAN_PHASE_SEGMENT2 6
#define CAN_DIVIDER 2
#define CAN_MIN_FREQUENCY 4
#endif /* CAN_SPEED == 100000 */
#if ( CAN_SPEED == 50000 )
#define CAN_PROP_SEGMENT 7
#define CAN_PHASE_SEGMENT1 6 /* = 13 */
#define CAN_PHASE_SEGMENT2 6
#define CAN_DIVIDER 4
#define CAN_MIN_FREQUENCY 4
#endif /* CAN_SPEED == 50000 */
#if ( CAN_SPEED == 25000 )
#define CAN_SYNCH_JUMP_WIDTH 2
#define CAN_PROP_SEGMENT 7
#define CAN_PHASE_SEGMENT1 6 /* = 13 */
#define CAN_PHASE_SEGMENT2 6
#define CAN_DIVIDER 8
#define CAN_MIN_FREQUENCY 4
#endif /* CAN_SPEED == 25000 */
#if ( CAN_SPEED == 10000 )
#define CAN_SYNCH_JUMP_WIDTH 2
#define CAN_PROP_SEGMENT 7
#define CAN_PHASE_SEGMENT1 6 /* = 13 */
#define CAN_PHASE_SEGMENT2 6
#define CAN_DIVIDER 20
#define CAN_MIN_FREQUENCY 4
#endif /* CAN_SPEED == 10000 */
#if CAN_OSCILLATOR_CLOCK < CAN_MIN_FREQUENCY
#error "incorrect CAN oscillator frequency for this CAN Speed"
#endif /* incorrect PLL_MUL */
#define CAN_SAMPLING 0
#ifndef CAN_SYNCH_JUMP_WIDTH
#define CAN_SYNCH_JUMP_WIDTH 1
#endif /* CAN_SAMPLING */
#if !defined(CAN_PRESCALER)
#define CAN_PRESCALER ( CAN_DIVIDER * CAN_OSCILLATOR_CLOCK / CAN_MIN_FREQUENCY )
#endif /* !defined(CAN_PRESCALER) */
#endif /* ifndef CAN_SPEED */
#if !defined(CAN_PROP_SEGMENT) || !defined(CAN_PHASE_SEGMENT1) || !defined(CAN_PHASE_SEGMENT2) || !defined(CAN_PRESCALER)
#error "CAN speed parameters( time segments and prescaler) are not correct assigned"
#endif /* !defined(CAN_PHASE_SEGMENT1) || !defined(CAN_PHASE_SEGMENT2) || !defined(CAN_PRESCALER) */
#if CAN_PHASE_SEGMENT1 + CAN_PROP_SEGMENT < 4 || CAN_PHASE_SEGMENT2 < 2
#error "time segments parameters are not supported by hardware implementation"
#endif /* CAN_PHASE_SEGMENT1 < 4 || CAN_PHASE_SEGMENT2 < 2 */
#if CAN_PRESCALER > 64
#error "invalid prescaler value or CAN oscillator frequency too high"
#endif /* CAN_PRESCALER > 64 */
#ifndef CAN_SAMPLING
#define CAN_SAMPLING 0
#endif /* CAN_SAMPLING */
#ifndef CAN_SYNCH_JUMP_WIDTH
#define CAN_SYNCH_JUMP_WIDTH 1
#endif /* CAN_SYNCH_JUMP_WIDTH */
/*** end of CAN Predefined speed / bit timing section ***/
#ifndef CAN_MAX_RECEIVE_ID
#define CAN_MAX_RECEIVE_ID 7
#endif /* ifdef CAN_MAX_RECEIVE_ID */
#ifndef CAN_MAX_TRANSMIT_ID
#define CAN_MAX_TRANSMIT_ID 7
#endif /* ifdef CAN_MAX_TRANSMIT_ID */
#ifndef CAN_STOP_IN_WAIT_MODE
#define CAN_STOP_IN_WAIT_MODE 0
#else /* ifndef CAN_STOP_IN_WAIT_MODE */
#undef CAN_STOP_IN_WAIT_MODE
#define CAN_STOP_IN_WAIT_MODE 1
#endif /* ifndef CAN_STOP_IN_WAIT_MODE */
#ifndef CAN_LOOP_BACK
#define CAN_LOOP_BACK 0
#else /* ifndef CAN_LOOP_BACK */
#undef CAN_LOOP_BACK
#define CAN_LOOP_BACK 1
#endif /* ifndef CAN_LOOP_BACK */
#ifndef CAN_WAKE_UP_MODE
#define CAN_WAKE_UP_MODE 0
#else /* ifndef CAN_WAKE_UP_MODE */
#undef CAN_WAKE_UP_MODE
#define CAN_WAKE_UP_MODE 1
#endif /* #ifndef CAN_WAKE_UP_MODE */
#if !defined(CAN_CUSTOM_FILTER_CODE)
#define CAN_CUSTOM_FILTER_CODE 0
#endif /* ifndef CAN_CUSTOM_FILTER_CODE */
#if !defined(CAN_CUSTOM_FILTER_MASK)
#define CAN_CUSTOM_FILTER_MASK 0x7FF
#endif /* ifndef CAN_CUSTOM_FILTER_MASK */
#endif /* INCLUDE_FLEXCAN */
/****************************************************************************
*
* Default PWM driver Initialization
*
****************************************************************************/
#ifdef INCLUDE_PWM
#if !defined(PWMA_CHANNEL_BUFFER_SIZE)
#define PWMA_CHANNEL_BUFFER_SIZE 32
#endif
#if !defined(PWMB_CHANNEL_BUFFER_SIZE)
#define PWMB_CHANNEL_BUFFER_SIZE 32
#endif
#define PWMA_BUF_SIZE (PWM_CLUSTER_SIZE * PWMA_CHANNEL_BUFFER_SIZE)
#define PWMB_BUF_SIZE (PWM_CLUSTER_SIZE * PWMB_CHANNEL_BUFFER_SIZE)
#endif
/****************************************************************************/
/****************************************************************************
*
* Default SCI driver Initialization
*
****************************************************************************/
#if defined( INCLUDE_SCI )
#if !defined(SCI0_RXBUF_SIZE)
#define SCI0_RXBUF_SIZE 32
#endif
#if !defined(SCI0_TXBUF_SIZE)
#define SCI0_TXBUF_SIZE 32
#endif
#if defined(BSP_DEVICE_NAME_SCI_1)
#if !defined(SCI1_RXBUF_SIZE)
#define SCI1_RXBUF_SIZE 32
#endif
#if !defined(SCI1_TXBUF_SIZE)
#define SCI1_TXBUF_SIZE 32
#endif
#endif
/* calculate SCI boud rate macro */
#define SCI_GET_SBR(BaudRate) (((((unsigned long)(PLL_MUL) * ((unsigned long)BSP_OSCILLATOR_FREQ)) \
+ (((unsigned long)BaudRate) * 32ul)) / \
(((unsigned long)BaudRate) * 64ul)) & 0x1fff)
#endif /* defined( INCLUDE_SCI ) */
/****************************************************************************
*
* Default DAC Configuration
*
****************************************************************************/
#if defined(INCLUDE_DAC)
#if !defined(DAC_CHANNEL_BUFFER_SIZE)
#define DAC_CHANNEL_BUFFER_SIZE 32
#endif
#define SPI0_BUF_SIZE (DAC_CLUSTER_SIZE * DAC_CHANNEL_BUFFER_SIZE)
ArchInstallCallback(Spi0, ChipSelect, dacSlaveSelect);
ArchInstallCallback(Spi0, ChipDeselect, dacSlaveDeselect);
ArchInstallCallback(Spi0, Tx, dacTxCallback);
#endif /* INCLUDE_DAC*/
/****************************************************************************
*
* Default SPI Configuration
*
****************************************************************************/
#if defined( INCLUDE_SPI )
/*SPI0*/
#if !defined( SPI0_BUF_SIZE )
#define SPI0_BUF_SIZE 32
#endif
/*SPI1*/
#if !defined( SPI1_BUF_SIZE )
#define SPI1_BUF_SIZE 32
#endif
/* calculate SPI baud rate macro */
#define SPI_BPS(divider) ( ( BSP_OSCILLATOR_FREQ * PLL_MUL / 2 / 2 ) / divider )
#define SPI_GET_DEGREE_SBR(BaudRate) BaudRate < SPI_BPS(256) ? 7 : \
BaudRate < SPI_BPS(128) ? 6 : \
BaudRate < SPI_BPS(64) ? 5 : \
BaudRate < SPI_BPS(32) ? 4 : \
BaudRate < SPI_BPS(16) ? 3 : \
BaudRate < SPI_BPS(8) ? 2 : \
BaudRate < SPI_BPS(4) ? 1 : 0
#define SPI_GET_SBR(BaudRate) ( (SPI_GET_DEGREE_SBR(BaudRate) ) << 13 )
#endif /* INCLUDE_SPI */
/****************************************************************************
*
* Default ADC Configuration
*
****************************************************************************/
#if defined( INCLUDE_ADC )
/* ADCA*/
#if !defined(ADCA_BUF_SIZE)
#define ADCA_BUF_SIZE 32
#endif
/* ADCB*/
#if !defined(ADCB_BUF_SIZE)
#define ADCB_BUF_SIZE 32
#endif
#define ADC_GET_FREQUENCY(BaudRate) ( ( BSP_OSCILLATOR_FREQ * PLL_MUL / 2 / 2 ) / (2*BaudRate) - 1 )
#endif /* INCLUDE_ADC*/
/* Base for buffers in P RAM (Dakar) */
#define P_MEMORY_BUFFER_BASE 0x02F800UL
/* buffers for modulo */
#define CUR_OFF 0
/*****************************************************************************/
/*****************************************************************************/
#undef BUF_BASE
#define BUF_BASE 10
/*****************************************************************************/
#if ( SCI0_RXBUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(SCI0_RXBUF_OFF)
#define SCI0_RXBUF_OFF CUR_OFF
enum __sci0RxEnum_BUF_BASE {SCI0_RXBUF_MASK = ( (2 << BUF_BASE) - 1 ), SCI0_RXBUF_OFFSET = SCI0_RXBUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( SCI0_RXBUF_OFFSET + SCI0_RXBUF_MASK + 1 )
#endif /* SCI0_RXBUF */
#if ( SCI0_TXBUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(SCI0_TXBUF_OFF)
#define SCI0_TXBUF_OFF CUR_OFF
enum __sci0TxEnum_BUF_BASE {SCI0_TXBUF_MASK = ( (2 << BUF_BASE) - 1 ), SCI0_TXBUF_OFFSET = CUR_OFF};
#undef CUR_OFF
#define CUR_OFF ( SCI0_TXBUF_OFFSET + SCI0_TXBUF_MASK + 1 )
#endif /* SCI0_TXBUF */
#if ( SCI1_RXBUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(SCI1_RXBUF_OFF)
#define SCI1_RXBUF_OFF CUR_OFF
enum __sci1RxEnum_BUF_BASE {SCI1_RXBUF_MASK = ( (2 << BUF_BASE) - 1 ), SCI1_RXBUF_OFFSET = SCI1_RXBUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( SCI1_RXBUF_OFFSET + SCI1_RXBUF_MASK + 1 )
#endif /* SCI1_RXBUF */
#if ( SCI1_TXBUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(SCI1_TXBUF_OFF)
#define SCI1_TXBUF_OFF CUR_OFF
enum __sci1TxEnum_BUF_BASE {SCI1_TXBUF_MASK = ( (2 << BUF_BASE) - 1 ), SCI1_TXBUF_OFFSET = SCI1_TXBUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( SCI1_TXBUF_OFFSET + SCI1_TXBUF_MASK + 1 )
#endif /* SCI1_TXBUF */
#if ( SPI0_BUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(SPI0_BUF_OFF)
#define SPI0_BUF_OFF CUR_OFF
enum __spi0Enum_BUF_BASE {SPI0_BUF_MASK = ( (2 << BUF_BASE) - 1 ), SPI0_BUF_OFFSET = SPI0_BUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( SPI0_BUF_OFFSET + SPI0_BUF_MASK + 1 )
#endif /* SPI0_BUF */
#if ( SPI1_BUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(SPI1_BUF_OFF)
#define SPI1_BUF_OFF CUR_OFF
enum __spi1Enum_BUF_BASE {SPI1_BUF_MASK = ( (2 << BUF_BASE) - 1 ), SPI1_BUF_OFFSET = SPI1_BUF_OFF};
#undef CURO_FF
#define CURO_FF ( SPI1_BUF_OFFSET + SPI1_BUF_MASK + 1 )
#endif /* SPI1_BUF */
#if ( ADCA_BUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(ADCA_BUF_OFF)
#define ADCA_BUF_OFF CUR_OFF
enum __adcAEnum_BUF_BASE {ADCA_BUF_MASK = ( (2 << BUF_BASE) - 1 ), ADCA_BUF_OFFSET = ADCA_BUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( ADCA_BUF_OFFSET + ADCA_BUF_MASK + 1 )
#endif /* ADCA_BUF */
#if ( ADCB_BUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(ADCB_BUF_OFF)
#define ADCB_BUF_OFF CUR_OFF
enum __adcBEnum_BUF_BASE {ADCB_BUF_MASK = ( (2 << BUF_BASE) - 1 ), ADCB_BUF_OFFSET = ADCB_BUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( ADCB_BUF_OFFSET + ADCB_BUF_MASK + 1 )
#endif /* ADCB_BUF */
#if ( PWMA_BUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(PWMA_BUF_OFF)
#define PWMA_BUF_OFF CUR_OFF
enum __pwmAEnum_BUF_BASE {PWMA_BUF_MASK = ( (2 << BUF_BASE) - 1 ), PWMA_BUF_OFFSET = PWMA_BUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( PWMA_BUF_OFFSET + PWMA_BUF_MASK + 1 )
#endif /* PWMA_BUF */
#if ( PWMB_BUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(PWMB_BUF_OFF)
#define PWMB_BUF_OFF CUR_OFF
enum __pwmBEnum_BUF_BASE {PWMB_BUF_MASK = ( (2 << BUF_BASE) - 1 ), PWMB_BUF_OFFSET = PWMB_BUF_OFF};
#undef CUR_OFF
#define CUR_OFF ( PWMB_BUF_OFFSET + PWMB_BUF_MASK + 1 )
#endif /* PWMB_BUF */
/*****************************************************************************/
#undef BUF_BASE
#define BUF_BASE 9
/*****************************************************************************/
#if ( SCI0_RXBUF_SIZE > (2 <<(BUF_BASE-1)) ) && !defined(SCI0_RXBUF_OFF)
#define SCI0_RXBUF_OFF CUR_OFF
enum __sci0RxEnum_BUF_BASE {SCI0_RXBUF_MASK = ( (2 << BUF_BASE) - 1 ), SCI0_RXBUF_OFFSET = SCI0_RXBUF_OFF};
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