config.c

56f8300E系列dsp的BOOTloader

#endif /* defined(DSP56838EVM) */

};


EXPORT void UserPreMain(void);
EXPORT void UserPostMain(void);
EXPORT void configInitialize(void);
EXPORT void configFinalize(void);

/*****************************************************************************/
EXPORT void configInitialize(void)
{

	#include "config.h"
	
/*****************************************************************************/
/* INCLUDE_BSP defaults to include the SIM, COP, CORE, PLL, and ITCN 
   initialization;  see configdefines.h for default BSP includes
*/


/*****************************************************************************/
#if defined( INCLUDE_SIM )
	{
//		simdrvInitialize(SIM_CONTROL_REG, SIM_CONFIG_REG, SIM_TEST_REG);
	}
#endif


/*****************************************************************************/
#if defined( INCLUDE_COP )
	{
//		copInitialize(COP_CONTROL_REG,COP_TIMEOUT_REG);
	}
#endif


/*****************************************************************************/
#if defined(INCLUDE_ADC)
{

		/* Clear Zero Crossing Control Reg */
		asm( clr.w		X:(BSP_PERIPH_BASE + archoff_AdcA_ZeroCrossControlReg) );
		/* clear channel reg */
		asm( clr.w		X:(BSP_PERIPH_BASE +archoff_AdcA_ChannelList1Reg) );
		asm( clr.w		X:(BSP_PERIPH_BASE +archoff_AdcA_ChannelList2Reg) );
		/* clear Limit Status Reg */
		asm( move.w		#0xFFFF , X:(BSP_PERIPH_BASE +archoff_AdcA_LimitStatusReg) );
		/* clear Zero Crossing Status Reg */
		asm( move.w		#0xFFFF , X:(BSP_PERIPH_BASE +archoff_AdcA_ZeroCrossStatusReg) );
		
		/* Clear Zero Crossing Control Reg */
		asm( clr.w		X:(BSP_PERIPH_BASE + archoff_AdcB_ZeroCrossControlReg) );
		/* clear channel reg */		
		asm( clr.w		X:(BSP_PERIPH_BASE +archoff_AdcB_ChannelList1Reg) );
		asm( clr.w		X:(BSP_PERIPH_BASE +archoff_AdcB_ChannelList2Reg) );
		/* clear Limit Status Reg */
		asm( move.w		#0xFFFF , X:(BSP_PERIPH_BASE +archoff_AdcB_LimitStatusReg) );
		/* clear Zero Crossing Status Reg */
		asm( move.w		#0xFFFF , X:(BSP_PERIPH_BASE +archoff_AdcB_ZeroCrossStatusReg) );		
}
#endif
/*****************************************************************************/


#if defined( INCLUDE_ITCN )
{	    
    enum tmpitcn { 
        itcn_off = (int) ( &((arch_sIO*)0)->IntCtrl.IntPriorityReg[0] ),
        
        itcn0 =  (ITCN_IPR_1 | ITCN_IPR_2 << 2 | ITCN_IPR_3 << 4 | ITCN_IPR_4 << 6 |  ITCN_IPR_5 << 8 
            | ITCN_IPR_6 << 10 | ITCN_IPR_7 << 12 | ITCN_IPR_8 << 14 ), 
        itcn1 =  (ITCN_IPR_9 | ITCN_IPR_10 << 2 | ITCN_IPR_11 << 4 | ITCN_IPR_12 << 6 | ITCN_IPR_13 << 8 
            | ITCN_IPR_14 << 10 | ITCN_IPR_15 << 12 | ITCN_IPR_16 << 14 ), 
        itcn2 =  (ITCN_IPR_17 | ITCN_IPR_18 << 2 | ITCN_IPR_19 << 4 | ITCN_IPR_20 << 6 | ITCN_IPR_21 << 8 
            | ITCN_IPR_22 << 10 | ITCN_IPR_23 << 12 | ITCN_IPR_24 << 14 ), 
        itcn3 =  (ITCN_IPR_25 | ITCN_IPR_26 << 2 | ITCN_IPR_27 << 4 | ITCN_IPR_28 << 6 | ITCN_IPR_29 << 8 
            | ITCN_IPR_30 << 10 | ITCN_IPR_31 << 12 | ITCN_IPR_32 << 14 ), 
        itcn4 =  (ITCN_IPR_33 | ITCN_IPR_34 << 2 | ITCN_IPR_35 << 4 | ITCN_IPR_36 << 6 | ITCN_IPR_37 << 8 
            | ITCN_IPR_38 << 10 | ITCN_IPR_39 << 12 | ITCN_IPR_40 << 14 ), 
        itcn5 =  (ITCN_IPR_41 | ITCN_IPR_42 << 2 | ITCN_IPR_43 << 4 | ITCN_IPR_44 << 6 | ITCN_IPR_45 << 8 
            | ITCN_IPR_46 << 10 | ITCN_IPR_47 << 12 | ITCN_IPR_48 << 14 ), 
        itcn6 =  (ITCN_IPR_49 | ITCN_IPR_50 << 2 | ITCN_IPR_51 << 4 | ITCN_IPR_52 << 6 | ITCN_IPR_53 << 8 
            | ITCN_IPR_54 << 10 | ITCN_IPR_55 << 12 | ITCN_IPR_56 << 14 ), 
        itcn7 =  (ITCN_IPR_57 | ITCN_IPR_58 << 2 | ITCN_IPR_59 << 4 | ITCN_IPR_60 << 6 | ITCN_IPR_61 << 8 
            | ITCN_IPR_62 << 10 | ITCN_IPR_63 << 12 | ITCN_IPR_64 << 14 ), 
        itcn8 =  (ITCN_IPR_65 | ITCN_IPR_66 << 2 | ITCN_IPR_67 << 4 | ITCN_IPR_68 << 6 | ITCN_IPR_69 << 8 
            | ITCN_IPR_70 << 10 | ITCN_IPR_71 << 12 | ITCN_IPR_72 << 14 ), 
        itcn9 =  (ITCN_IPR_73 | ITCN_IPR_74 << 2 | ITCN_IPR_75 << 4 | ITCN_IPR_76 << 6 | ITCN_IPR_77 << 8 
            | ITCN_IPR_78 << 10 | ITCN_IPR_79 << 12 | ITCN_IPR_80 << 14 )   
    };

    asm( move.w #itcn0, X:(BSP_PERIPH_BASE + itcn_off + 0) ); 
    asm( move.w #itcn1, X:(BSP_PERIPH_BASE + itcn_off + 1) ); 
    asm( move.w #itcn2, X:(BSP_PERIPH_BASE + itcn_off + 2) ); 
    asm( move.w #itcn3, X:(BSP_PERIPH_BASE + itcn_off + 3) ); 
    asm( move.w #itcn4, X:(BSP_PERIPH_BASE + itcn_off + 4) ); 
    asm( move.w #itcn5, X:(BSP_PERIPH_BASE + itcn_off + 5) ); 
    asm( move.w #itcn6, X:(BSP_PERIPH_BASE + itcn_off + 6) ); 
    asm( move.w #itcn7, X:(BSP_PERIPH_BASE + itcn_off + 7) ); 
    asm( move.w #itcn8, X:(BSP_PERIPH_BASE + itcn_off + 8) ); 
    asm( move.w #itcn9, X:(BSP_PERIPH_BASE + itcn_off + 9) ); 

	}
#endif

/*****************************************************************************/
#ifdef INCLUDE_DSPFUNC
	dspfuncInitialize();
#endif
/*****************************************************************************/


/*****************************************************************************/
#if defined( INCLUDE_STACK_CHECK )
	{
		stackcheckInitialize ();
	}
#endif	


/*****************************************************************************/
/* This must be the last line config procidure                               */

#if defined( INCLUDE_CORE )
	{
		if (BSP_ENABLE_INTERRUPTS)
		{			
			archEnableInt();
		}
	}
#endif

/*****************************************************************************/

#if defined( INCLUDE_GPIO )
	{
        gpioCreate();
	}
#endif /* INCLUDE_GPIO */

/*****************************************************************************/

#if defined( INCLUDE_DECODER )
    {
        decoderCreate(NULL);
    }
#endif /* INCLUDE_DECODER */

/*****************************************************************************/
#if defined( INCLUDE_MSCAN )
    {
    	extern const can_sInitialState canInitialState;
		CANDevCreat(&canInitialState);
    }
#endif 


/*****************************************************************************/
#if defined( INCLUDE_FLEXCAN )
    {
		FC_Init();
    #if defined(CAN_RAW_CALLBACK)
        FC_InitCallBack(  ~CAN_CUSTOM_FILTER_MASK, CAN_CUSTOM_FILTER_CODE );
    #endif  /* ifndef CAN_RAW_CALLBACK  */
    }
#endif 


/*****************************************************************************/
#if defined( INCLUDE_TIMER )
	{

		extern const posix_tConfig posixDeviceMap[];

        timerCreate(/* (const char *) posixDeviceMap[0].ctx  */);
        

	}
#endif

/*****************************************************************************/
#if defined ( INCLUDE_PWM)
	{
		#ifdef BSP_DEVICE_NAME_PWM_B				
			pwmCreate(BSP_DEVICE_NAME_PWM_A);
		#endif
		#ifdef BSP_DEVICE_NAME_PWM_B
				pwmCreate(BSP_DEVICE_NAME_PWM_B);
		#endif
	}

#endif

}



/*****************************************************************************/
void configFinalize(void)
{
	// UserPostMain();
}
#if defined( INCLUDE_SCI )
unsigned long sci_getBaudRate( unsigned long BaudRate)
{  // use const array for future 
/* DSP56838EVM oscillator frequency is 8.0MHz */
	return  SCI_GET_SBR(BaudRate);
}
#endif /* defined( INCLUDE_SCI ) */

#if defined( INCLUDE_SPI )
unsigned long spi_getBaudRate( unsigned long BaudRate)
{  // use const array for future 
/* DSP56838EVM oscillator frequency is 8.0MHz */
	return  SPI_GET_SBR(BaudRate);
}
#endif /* defined( INCLUDE_SPI ) */

#if defined( INCLUDE_ADC )
unsigned long adc_getBaudRate( unsigned long BaudRate)
{  
	short divider = ADC_GET_FREQUENCY(BaudRate);
	
	if(divider < 0) divider = 0;
	if(divider > 31) divider = 31;
	
	return  divider;
}
#endif /* defined( INCLUDE_ADC ) */