📄 config.c
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/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
* $Element: /project/dsp568_sdk/sdk/src/dsp56838evm/nos/config/config.c $
* $Author: saa $
* $Revision: /main/2 $
* $VOB: /project/dsp568_sdk $
* $OS: solaris $
*
* Description: configuration of SDK application
*
* Notes: dynamic statement mostly
*
******************************************************************************/
#define INCLUDE_PLL
#include "port.h"
#include "bsp.h"
#include "arch.h"
#include "arch_off.h"
#include "periph.h"
#include "pll.h"
#include "timerdrv.h"
#include "gpiodrv.h"
#include "scidrv.h"
#if defined(DSP56838EVM)
#include "mscan.h"
#else /* defined(DSP56838EVM) */
#include "flexcan.h"
#endif /* defined(DSP56838EVM) */
//#include "dspfunc.h"
#include "string.h"
#define ArchInstallISR( num, CallBack, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchInstallFastISR( num, CallBack, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchInstallCallBackISR(device,num, type, CallBack, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchInstall2CallBackISR(device,num, type1, type2, CallBack, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchInstall4CallBackISR(device,num, type1, type2, type3, type4, CallBack, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchInstallSuperFastISR0( num, CallBack ) enum tmpitcn##num { ITCN_IPR_##num = 2, ITCN_F0 = num * 2 }
#define ArchInstallSuperFastISR1( num, CallBack ) enum tmpitcn##num { ITCN_IPR_##num = 2, ITCN_F1 = num * 2 }
#define ArchInstallTimerISR( num, tmr, chnl, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchInstallADCErrorCallBackISR(device, num, CallBack, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchInstallGPIOISR( num, port, prio ) enum tmpitcn##num { ITCN_IPR_##num = prio }
#define ArchQuadCallBackOnCpmpare(tmr, chnl, CallBack ) extern void SDK_stb(void)
#define ArchQuadCallBackOnOverflow(tmr, chnl, CallBack ) extern void SDK_stb(void)
#define ArchQuadCallBackOnInputEdge(tmr, chnl, CallBack ) extern void SDK_stb(void)
#define ArchInstallCallback(device, type, CallBack ) extern void SDK_stb(void)
#define ArchParameter(adc, ...) enum adc##_VALUE {__VA_ARGS__ }
enum ITCNVALUE {
#if defined(DSP56838EVM)
ITCN_IPR_1 = 3, /* n/a */
ITCN_IPR_2 = 3, /* n/a */
ITCN_IPR_3 = 3, /* n/a */
ITCN_IPR_4 = 3, /* n/a */
ITCN_IPR_5 = 3, /* n/a */
ITCN_IPR_6 = 1, /*(0:10) EOnCE Step Counter */
ITCN_IPR_7 = 1, /*(0:12) EOnCE Breakpoint Unit 0 */
ITCN_IPR_8 = 1, /* n/a */
ITCN_IPR_9 = 1, /*(1:0) EOnCE Trace Buffer Interrupt Priority Level */
ITCN_IPR_10 = 1, /*(1:2) EOnCE Transmit Register Empty */
ITCN_IPR_11 = 1, /*(1:4) EOnCE Receive Register Full */
ITCN_IPR_12 = 0, /* n/a */
ITCN_IPR_13 = 0, /* n/a */
ITCN_IPR_14 = 0, /* n/a */
ITCN_IPR_15 = 0, /* n/a */
ITCN_IPR_16 = 0, /* n/a */
ITCN_IPR_17 = 0, /*(2:0) IRQA */
ITCN_IPR_18 = 0, /*(2:2) IRQB */
ITCN_IPR_19 = 0, /* n/a */
ITCN_IPR_20 = 0, /*(2:6) PLL Loss of Lock */
ITCN_IPR_21 = 0, /* n/a */
ITCN_IPR_22 = 0, /*(2:10) HFM Error Interrupt */
ITCN_IPR_23 = 0, /*(2:12) HFM Command complete */
ITCN_IPR_24 = 0, /*(2:14) HFM Command Data & Address Buffers Empty */
ITCN_IPR_25 = 0, /* n/a */
ITCN_IPR_26 = 0, /*(3:2) MSCAN Transmitter Ready or FlexCAN bus-off */
ITCN_IPR_27 = 0, /*(3:4) MSCAN Wake-up or FlexCAN wake-up */
ITCN_IPR_28 = 0, /*(3:6??) MSCAN recv full int or FlexCAN msg buff int */
ITCN_IPR_29 = 0, /*(3:8??) ???? MSCAN Receiver Full Interrupt OR FlexCAN Message Buffer Interrupt*/
ITCN_IPR_30 = 0, /*(3:10) GPIO E */
ITCN_IPR_31 = 0, /*(3:12) GPIO D */
ITCN_IPR_32 = 0, /*(3:14) GPIO C */
ITCN_IPR_33 = 0, /*(4:0) GPIO B */
ITCN_IPR_34 = 0, /*(4:2) GPIO A */
ITCN_IPR_35 = 0, /* n/a */
ITCN_IPR_36 = 0, /* n/a */
ITCN_IPR_37 = 0, /*(4:8) Low Voltage Detector */
ITCN_IPR_38 = 0, /*(4:10) SPI 1 Receiver Full */
ITCN_IPR_39 = 0, /*(4:12) SPI 1 Transmitter Empty */
ITCN_IPR_40 = 0, /*(4:14) SPI 0 Receiver Full */
ITCN_IPR_41 = 0, /*(5:0) SPI 0 Transmitter Empty */
ITCN_IPR_42 = 0, /*(5:2) SCI 1 Transmitter Empty */
ITCN_IPR_43 = 0, /*(5:4) SCI 1 Transmitter Idle */
ITCN_IPR_44 = 0, /*(5:4) SCI 1 Receiver Idle */
ITCN_IPR_45 = 0, /*(5:8) SCI 1 Receiver Error*/
ITCN_IPR_46 = 0, /*(5:10) SCI 1 Receiver Full */
ITCN_IPR_47 = 0, /* n/a */
ITCN_IPR_48 = 0, /* n/a */
ITCN_IPR_49 = 0, /*(6:0) Quadrature Decoder #0 Home Switch or Watchdo*/
ITCN_IPR_50 = 0, /*(6:2) Quadrature Decoder #0 Index Pulse */
ITCN_IPR_51 = 0, /* n/a */
ITCN_IPR_52 = 0, /*(6:6) Timer D Channel 0 */
ITCN_IPR_53 = 0, /*(6:8) Timer D Channel 1 */
ITCN_IPR_54 = 0, /*(6:10) Timer D Channel 2 */
ITCN_IPR_55 = 0, /*(6:12) Timer D Channel 3 */
ITCN_IPR_56 = 0, /*(6:14) Timer C Channel 0 */
ITCN_IPR_57 = 0, /*(7:0) Timer C Channel 1 */
ITCN_IPR_58 = 0, /*(7:2) Timer C Channel 2 */
ITCN_IPR_59 = 0, /*(7:4) Timer C Channel 3 */
ITCN_IPR_60 = 0, /*(7:6) Timer A Channel 0 */
ITCN_IPR_61 = 0, /*(7:8) Timer A Channel 1 */
ITCN_IPR_62 = 0, /*(7:10) Timer A Channel 2 */
ITCN_IPR_63 = 0, /*(7:12) Timer A Channel 3 */
ITCN_IPR_64 = 0, /*(7:14) SCI 0 Transmitter Empty */
ITCN_IPR_65 = 0, /*(8:0) SCI 0 Transmitter Idle */
ITCN_IPR_66 = 1, /*(8:4) SCI 0 Receiver Idle */
ITCN_IPR_67 = 0, /*(8:4) SCI 0 Receiver Error */
ITCN_IPR_68 = 0, /*(8:6) SCI 0 Receiver Full */
ITCN_IPR_69 = 0, /*(8:8) ADC B Conversion Complete */
ITCN_IPR_70 = 0, /*(8:10) ADC A Conversion Complete */
ITCN_IPR_71 = 0, /*(8:12) ADC B Zero Crossing or Limit Error */
ITCN_IPR_72 = 0, /*(8:14) ADC A Zero Crossing or Limit Error */
ITCN_IPR_73 = 0, /*(9:0) Reload PWM B */
ITCN_IPR_74 = 0, /*(9:2) Reload PWM A */
ITCN_IPR_75 = 0, /*(9:4) PWM B Fault */
ITCN_IPR_76 = 0, /*(9:6) PWM A Fault */
ITCN_IPR_77 = 0, /* n/a */
ITCN_IPR_78 = 0, /* n/a */
ITCN_IPR_79 = 0, /* n/a */
ITCN_IPR_80 = 0, /* n/a */
ITCN_IPR_81 = 0 /* n/a */
#else /* defined(DSP56838EVM) */
ITCN_IPR_1 = 3, /* n/a */
ITCN_IPR_2 = 3, /* n/a */
ITCN_IPR_3 = 3, /* n/a */
ITCN_IPR_4 = 3, /* n/a */
ITCN_IPR_5 = 3, /* n/a */
ITCN_IPR_6 = 1, /*(0:10) EOnCE Step Counter */
ITCN_IPR_7 = 1, /*(0:12) EOnCE Breakpoint Unit 0 */
ITCN_IPR_8 = 1, /* n/a */
ITCN_IPR_9 = 1, /*(1:0) EOnCE Trace Buffer Interrupt Priority Level */
ITCN_IPR_10 = 1, /*(1:2) EOnCE Transmit Register Empty */
ITCN_IPR_11 = 1, /*(1:4) EOnCE Receive Register Full */
ITCN_IPR_12 = 0, /* n/a */
ITCN_IPR_13 = 0, /* n/a */
ITCN_IPR_14 = 0, /* n/a */
ITCN_IPR_15 = 0, /* n/a */
ITCN_IPR_16 = 0, /* n/a */
ITCN_IPR_17 = 0, /*(2:0) IRQA */
ITCN_IPR_18 = 0, /*(2:2) IRQB */
ITCN_IPR_19 = 0, /* n/a */
ITCN_IPR_20 = 0, /*(2:6) Low Voltage Detector */
ITCN_IPR_21 = 0, /*(2:8) PLL Loss of Lock */
ITCN_IPR_22 = 0, /*(2:10) HFM Error Interrupt */
ITCN_IPR_23 = 0, /*(2:12) HFM Command complete */
ITCN_IPR_24 = 0, /*(2:14) HFM Command Data & Address Buffers Empty */
ITCN_IPR_25 = 0, /* n/a */
ITCN_IPR_26 = 0, /*(3:2) FlexCAN bus-off */
ITCN_IPR_27 = 0, /*(3:4) FlexCAN error */
ITCN_IPR_28 = 0, /*(3:6) FlexCAN wake-up */
ITCN_IPR_29 = 0, /*(3:8) FlexCAN Message Buffer Interrupt*/
ITCN_IPR_30 = 0, /*(3:10) GPIO F */
ITCN_IPR_31 = 0, /*(3:12) GPIO E */
ITCN_IPR_32 = 0, /*(3:14) GPIO D */
ITCN_IPR_33 = 0, /*(4:0) GPIO C */
ITCN_IPR_34 = 0, /*(4:2) GPIO B */
ITCN_IPR_35 = 0, /*(4:4) GPIO A */
ITCN_IPR_36 = 0, /* n/a */
ITCN_IPR_37 = 0, /* n/a */
ITCN_IPR_38 = 0, /*(4:10) SPI 1 Receiver Full */
ITCN_IPR_39 = 0, /*(4:12) SPI 1 Transmitter Empty */
ITCN_IPR_40 = 0, /*(4:14) SPI 0 Receiver Full */
ITCN_IPR_41 = 0, /*(5:0) SPI 0 Transmitter Empty */
ITCN_IPR_42 = 0, /*(5:2) SCI 1 Transmitter Empty */
ITCN_IPR_43 = 0, /*(5:4) SCI 1 Transmitter Idle */
ITCN_IPR_44 = 0, /*(n/a) */
ITCN_IPR_45 = 0, /*(5:8) SCI 1 Receiver Error*/
ITCN_IPR_46 = 0, /*(5:10) SCI 1 Receiver Full */
ITCN_IPR_47 = 0, /*(5:12) */
ITCN_IPR_48 = 0, /*(5:14) */
ITCN_IPR_49 = 0, /*(6:0) Quadrature Decoder #0 Home Switch or Watchdo*/
ITCN_IPR_50 = 0, /*(6:2) Quadrature Decoder #0 Index Pulse */
ITCN_IPR_51 = 0, /* n/a */
ITCN_IPR_52 = 0, /*(6:6) Timer D Channel 0 */
ITCN_IPR_53 = 0, /*(6:8) Timer D Channel 1 */
ITCN_IPR_54 = 0, /*(6:10) Timer D Channel 2 */
ITCN_IPR_55 = 0, /*(6:12) Timer D Channel 3 */
ITCN_IPR_56 = 0, /*(6:14) Timer C Channel 0 */
ITCN_IPR_57 = 0, /*(7:0) Timer C Channel 1 */
ITCN_IPR_58 = 0, /*(7:2) Timer C Channel 2 */
ITCN_IPR_59 = 0, /*(7:4) Timer C Channel 3 */
ITCN_IPR_60 = 0, /*(7:6) Timer B Channel 0 */
ITCN_IPR_61 = 0, /*(7:8) Timer B Channel 1 */
ITCN_IPR_62 = 0, /*(7:10) Timer B Channel 2 */
ITCN_IPR_63 = 0, /*(7:12) Timer B Channel 3 */
ITCN_IPR_64 = 0, /*(7:14) Timer A Channel 0 */
ITCN_IPR_65 = 0, /*(8:0) Timer A Channel 1 */
ITCN_IPR_66 = 0, /*(8:2) Timer A Channel 2 */
ITCN_IPR_67 = 0, /*(8:4) Timer A Channel 3 */
ITCN_IPR_68 = 0, /*(8:6) SCI 0 Transmitter Empty */
ITCN_IPR_69 = 0, /*(8:8) SCI 0 Transmitter Idle */
ITCN_IPR_70 = 1, /* n/a */
ITCN_IPR_71 = 0, /*(8:12) SCI 0 Receiver Error */
ITCN_IPR_72 = 0, /*(8:14) SCI 0 Receiver Full */
ITCN_IPR_73 = 0, /*(9:0) ADC B Conversion Complete */
ITCN_IPR_74 = 0, /*(9:2) ADC A Conversion Complete */
ITCN_IPR_75 = 0, /*(9:4) ADC B Zero Crossing or Limit Error */
ITCN_IPR_76 = 0, /*(9:6) ADC A Zero Crossing or Limit Error */
ITCN_IPR_77 = 0, /*(9:8) Reload PWM B */
ITCN_IPR_78 = 0, /*(9:10) Reload PWM A */
ITCN_IPR_79 = 0, /*(9:12) PWM B Fault */
ITCN_IPR_80 = 0, /*(9:14) PWM A Fault */
ITCN_IPR_81 = 0 /* n/a */
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