mscan.h

56f8300E系列dsp的BOOTloader

#ifndef MSCAN_H
#define MSCAN_H
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
********************************************************************************
*
* FILE NAME: mscan.h
*
*******************************************************************************/


/*** CAN driver configuration issue ***/
/** Use this macro definitions to choose needed CAN driver configuration */


/* #undef CAN20B 1  */


#ifdef __cplusplus
extern "C" {
#endif

#include "can.h"
#include "io.h"

#if defined( CAN20B )             

typedef UWord32 CANADDRESSTYPE;     /* CAN2.0B addressing mode */

#define CANFILTERMODE  0x0000       /* value for CIDAR */
#define CANFILTERLIMIT 2            /* 2 filters */
#define CANIDMASK 0x01FFFFFFF       /* 29-bit CAN ID */
#define CANIDSIZE 29                /* 29-bit CAN ID */   

#else /* defined( CAN20B ) */   

typedef UWord16 CANADDRESSTYPE;     /* CAN2.0A addressing mode */

#define CANFILTERMODE  0x0010       /* value for CIDAR */
#define CANFILTERLIMIT 4            /* 4 filters */
#define CANIDMASK 0x07FF            /* 11-bit CAN ID */
#define CANIDSIZE 11                /* 11-bit CAN ID */

#endif /* defined( CAN20B ) */


/*** MSCAN Masks for registers ***/

/* CMCR0 - Module Control Register 0 */
#define CANSFTRES       0x01    /* Software Reset */ 
#define CANSLPRQ        0x02    /* Sleep Mode Request */
#define CANSLPAK        0x04    /* Sleep Mode Acknowledge (READ ONLY) */
#define CANTLNKE        0x08    /* Timer Enable */
#define CANSYNCH        0x10    /* Synchronized status (READ ONLY) */
#define CANCSWAI        0x20    /* CAN Stops in Wait Mode */

/* CMCR1 - Module Control Register 1 */
#define CANCLKSRC       0x01    /* Clock Source (PLL or crystal oscillator) */
#define CANWUPM         0x02    /* Wake-Up mode */
#define CANLOOPB        0x04    /* Loop Back Self Test mode */
#define CANCANE         0x80    /* CAN Enable */


/* CBTR0 - Bus Timing Register 0 */
#define CANSJW          0xC0    /* Re-Synchronization Jump Width */
#define CANBRP          0x3F    /* Baud Rate Prescaler */

/* CBTR1 - Bus Timing Register 1 */
#define CANSAMP         0x80    /* Sample Mode */
#define CANTSEG2        0x70    /* Time Segment 2 duration */
#define CANTSEG1        0x0F    /* Time Segment 1 duration */

/* CRFLG - Receiver Flag Register */
#define CANWUPIF        0x80    /* Wake-up Interrupt Flag */
#define CANRWRNIF       0x40    /* Receiver Warning Interrupt Flag */
#define CANTWRNIF       0x20    /* Transmitter Warning Interrupt Flag */
#define CANRERRIF       0x10    /* Receiver Error Passive Interrupt Flag */
#define CANTERRIF       0x08    /* Transmitter Error Passive Interrupt Flag */
#define CANBOFFIF       0x04    /* Bus-Off Interrupt Flag */
#define CANOVRIF        0x02    /* Overrun Interrupt Flag */
#define CANRXF          0x01    /* Receive Buffer Full */

/* CRIER - Receiver Interrupt Enable Register */
#define CANWUPIE        0x80    /* Wake-up Interrupt Enable */
#define CANRWRNIE       0x40    /* Receiver Warning Interrupt Enable */
#define CANTWRNIE       0x20    /* Transmitter Warning Interrupt Enable */
#define CANRERRIE       0x10    /* Receiver Error Passive Interrupt Enable */
#define CANTERRIE       0x08    /* Transmitter Error Passive Interrupt Enable */
#define CANBOFFIE       0x04    /* Bus-Off Interrupt Enable */
#define CANOVRIE        0x02    /* Overrun Interrupt Enable */
#define CANRXFIE        0x01    /* Receiver Full Interrupt Enable */    
     
/* CTFLG - Transmitter Flag Register */
#define CANABTAK2       0x40    /* Abort Acknowledge for Tx buffer 2 */
#define CANABTAK1       0x20    /* Abort Acknowledge for Tx buffer 1 */
#define CANABTAK0       0x10    /* Abort Acknowledge for Tx buffer 0 */
#define CANTXE2         0x04    /* Transmit buffer 2 empty */
#define CANTXE1         0x02    /* Transmit buffer 1 empty */
#define CANTXE0         0x01    /* Transmit buffer 0 empty */
      
/* CTCR - Transmitter Control Register */
#define CANABTRQ2       0x40    /* Abort Request for Tx buffer 2 */
#define CANABTRQ1       0x20    /* Abort Request for Tx buffer 1 */
#define CANABTRQ0       0x10    /* Abort Request for Tx buffer 0 */
#define CANTXEIE2       0x04    /* Transmit buffer 2 empty interrupt enable */
#define CANTXEIE1       0x02    /* Transmit buffer 1 empty interrupt enable */
#define CANTXEIE0       0x01    /* Transmit buffer 0 empty interrupt enable */

/* CIDAC - Identifier Acceptance Control register */
#define CANIDAM0        0x10    /* Identifier Acceptance mode settings (0) */
#define CANIDAM1        0x20    /* Identifier Acceptance mode settings (1) */
#define CANIDHIT1       0x02    /* Identifier Acceptance Hit Indicator */
#define CANIDHIT0       0x01    /* (READ ONLY bits) */


/*** Driver Flags ***/
#define CANWATCHFLAG   ( CANTERRIF | CANTWRNIE | CANBOFFIE ) /* process flags */
#define CANERRORFLAG   ( CANOVRIE | CANBOFFIE | CANTERRIE | CANRERRIE | CANTWRNIE | CANRWRNIE )

/* Temporary masks */
#define CANMSPROPMASK 0x07      
#define CANLOWESTPRIO 0x7F      

/* iaxxbyyy - 8 bit value returned by CANDll() 
 i  - tx isr needed
 a  - all free
 xx - buffer index: 0, 1, 2 
 b  - all busy
 yyy - bit position of buffer in CTCR & CTFLG regs: 0x01, 0x02, 0x04 */

#define CANM_FREE0  0x00    /* 0th buffer is free */
#define CANM_FREE1  0x10    /* 1st buffer is free */
#define CANM_FREE2  0x20    /* 2nd buffer is free */
#define CANM_ALLFREE 0x40   /* All buffers are free */
#define CANM_ALLBUSY 0x08   /* All buffers busy */
#define CANM_TXISR  0x80    /* More than 1 buffer busy - ISR needed */

/* MSCAN filter support */ 
struct CANFilterMirror
{
    CANADDRESSTYPE  code;
    CANADDRESSTYPE  mask;
};

enum eTypeOfBuffers 
{
    CAN_IDX_BUF0        =   0x0001,  /* CAN buffer ID */
    CAN_IDX_BUF1        =   0x0002,
    CAN_IDX_BUF2        =   0x0004,

    CAN_BUF_EMPTY       =   0x0000,  /* Rx message buffer is empty */
    CAN_BUF_PENDING     =   0x0010,  /* Tx message buffer is transmitting */
    CAN_BUF_FULL        =   0x0020,  /* Rx message buffer is full */
    CAN_BUF_OVERFLOW    =   0x0040,  /* Rx message buffer data is overwritten */
    CAN_BUF_ERROR       =   0x0080,  /* Tx message buffer was not transmitted */

    CAN_BUF_READ_HANDLE =   0x0100,  
    CAN_BUF_SYNCHRONOUS =   0x0200,
    CAN_BUF_PRIORITY_SCHEDULE = 0x0400,
/*    CAN_BUF_IO_DATAFORMAT_RAW = 0x0800, */

/* Reserved bit instead of type opening a buffer */
    CAN_BUF_FREE     	= 	0x8000 
};

typedef struct                              /* message buffer for receiving */
{
    io_sInterface *     drvInterface;
    UWord16             flags;              /* current status */
    CANADDRESSTYPE      canID;              /* CAN ID */
    can_sData           data[1];            /* received data - extended for que mode */
}can_sReadBuffer;


typedef struct _can_sWriteBuffer      /* message buffer for sending */
{
    io_sInterface *         drvInterface;
    UWord16                 flags;    /* current status */
    CANADDRESSTYPE          canID;    /* CAN ID */
    UWord16                 priority;
}can_sWriteBuffer;



#define CAN_LOG( value )                          \
(           (value) > 8?                          \
                (value) > 32 ?                    \
                    (value) > 64 ? 7 : 6          \
                :       (value) > 16 ? 5 : 4      \
            :   (value) > 2  ?                    \
                    (value) > 4 ? 3 : 2           \
                :       (value) > 1 ? 1 : 0  )


#define CAN_ROUND2UP( value )   ( 1 << CAN_LOG( value ) )

#define CAN_RX_BUFFER_SIZE( que )       \
 (   sizeof(can_sReadBuffer) + ( CAN_ROUND2UP(que) - 1) * sizeof(can_sData)   )  


typedef struct               			/* MSCAN initializing structure */  
{
    const char* pName;                  /* name of the device */  

    can_sReadBuffer* pRxBuffer;         /* Rx buffers */ 
    can_sReadBuffer* pLastRx;           /* Rx buffers */ 
    UWord16  RxSize;                    /* max number of Tx buffers */ 

    can_sWriteBuffer* pTxBuffer;        /* Tx buffers */
    can_sWriteBuffer* pLastTx;          /* last pointer */

    can_pRawCallBack pRawCallBack;      /* custom callback */
    
    UWord16 regCMCR0;                   /* CMCR0 initial value: CSWAI is actual */
    UWord16 regCMCR1;                   /* CMCR1 initial value: LOOPB, WUPM, CLKSRC */
    UWord16 regCBTR0;                   /* CBTR0 initial value */ 
    UWord16 regCBTR1;                   /* CBTR1 initial value */

    UWord32 code;                       /* acceptance code initial value, valid if not exeeds the CANID size */  
    UWord32 mask;                       /* acceptance code initial value, valid if not exeeds the CANID size */ 
    
    UWord16 queMask;                    /* Rx queue mask */

    UWord16 TxAssert;                   /* assert flag for synch mode */

}can_sInitialState;


EXPORT UWord16 CANDevCreat(const can_sInitialState* pInitialState); /* MSCAN driver install */

void CANReceiveISR(void);
void CANSendISR(void);
void CANWakeUpISR(void);
void CANErrorISR(void);
/* void CANReceiveSuperISR(void); */

typedef const struct 
{
	ssize_t  (*pRead)(handle_t hndl, void *buf, size_t);
	ssize_t  (*pWrite)(handle_t hndl, const void *buf, size_t len);
	int      (*pClose)(handle_t hndl);
	UWord16  (*pIoctl[5])(handle_t hndl, void *pParams );
} io_sMSCANInterface;


handle_t     canOpen(const char * pName, int oFlags, ...);
int 		 canClose(handle_t FileDesc);
ssize_t      canRead(handle_t FileDesc,void *pBuffer, size_t size);
ssize_t 	 canWrite(handle_t FileDesc, const void *pBuffer, size_t size);

UWord16 ioctlCAN_RESET       (handle_t FileDesc, void * pParams );
UWord16 ioctlCAN_SET_SLEEP   (handle_t FileDesc, void * pParams );
UWord16 ioctlCAN_SET_WAKEUP  (handle_t FileDesc, void * pParams );
UWord16 ioctlCAN_GET_STATUS  (handle_t FileDesc, void * pParams );
UWord16 ioctlCANID_GET_STATUS(handle_t FileDesc, void * pParams );

can_sData* CANStdRcvPrepare( CANADDRESSTYPE canID );


#ifdef __cplusplus
}
#endif

#endif /* MSCAN_H */