📄 const.c
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const io_sInterface scidrvIONonBlockInterfaceVT =
{
noSciNonBlockRead, noSciNonBlockWrite, noSciClose, noSciIoctl
};
#endif /* INCLUDE_IO */
#if defined(BSP_DEVICE_NAME_SCI_0)
struct sSciDevice Sci0DeviceContext =
{
(io_sInterface *)&scidrvIONonBlockInterfaceVT,
&ArchIO.Sci0, /* Base */
SCI_SCIDR_8BIT_MASK, /* Mask */
/* receive */
{
0, /* begin */
0, /* marker*/
SCI0_RXBUF_MASK, /* mask */
SCI0_RXBUF_OFFSET /* buffer address */
},
/* send */
{
0, /* begin */
0, /* marker*/
SCI0_TXBUF_MASK, /* mask */
SCI0_TXBUF_OFFSET /* buffer address */
}
};
#endif
#if defined(BSP_DEVICE_NAME_SCI_1)
struct sSciDevice Sci1DeviceContext =
{
(io_sInterface *)&scidrvIONonBlockInterfaceVT,
&ArchIO.Sci1, /* Base */
SCI_SCIDR_8BIT_MASK, /* Mask */
/*receive*/
{
0, /* begin */
0, /* marker*/
SCI1_RXBUF_MASK, /* mask */
SCI1_RXBUF_OFFSET /* buffer address */
},
/*send*/
{
0, /* begin */
0, /* marker*/
SCI1_TXBUF_MASK, /* mask */
SCI1_TXBUF_OFFSET /* buffer address */
}
};
#endif /* defined(BSP_DEVICE_NAME_SCI_1) */
#endif /* INCLUDE_SCI */
/*****************************************************************************/
#if defined( INCLUDE_DECODER )
const io_sDecoderInterface decoderdrvIOInterfaceVT = {
NULL,
NULL,
decoderClose,
{
decoderIoctlDEC_HOME_INTERRUPT_REQUEST_CLEAR,
decoderIoctlDEC_INDEX_PULSE_INTERRUPT_REQUEST_CLEAR,
decoderIoctlDEC_WATCHDOG_INTERRUPT_REQUEST_CLEAR,
decoderIoctlDEC_WRITE_WATCHDOG_TIMEOUT,
decoderIoctlDEC_READ_POSITION_DIFFERENCE,
decoderIoctlDEC_READ_REVOLUTION,
decoderIoctlDEC_WRITE_REVOLUTION,
decoderIoctlDEC_READ_POSITION,
decoderIoctlDEC_WRITE_POSITION,
decoderIoctlDEC_WRITE_INIT_STATE,
decoderIoctlDEC_READ_MONITOR_REG,
decoderIoctlDEC_GET_RAW_ENCSIGNALS,
decoderIoctlDEC_GET_FILTERED_ENCSIGNALS,
decoderIoctlDEC_READ_CONTROL_REG,
decoderIoctlDEC_CALCULATE_SCALE_COEF,
decoderIoctlDEC_GET_SCALED_POSITION,
decoderIoctlDEC_GET_SCALED_POSITION_DIFFERENCE,
}
};
sDecoderDevice Decoder0DeviceContext =
{
(io_sInterface *)&decoderdrvIOInterfaceVT,
0,
0,
0,
0,
0
};
#endif /* defined( INCLUDE_DECODER ) */
/*****************************************************************************/
#if defined( INCLUDE_GPIO )
const io_sGPIOInterface gpiodrvIOInterfaceVT = {
gpioRead,
gpioWrite,
gpioClose,
#if defined( GPIO_INLINE )
NULL,
#else
{
gpioIoctlGPIO_SET,
gpioIoctlGPIO_CLEAR,
gpioIoctlGPIO_TOGGLE,
gpioIoctlGPIO_DISABLE_PULLUP,
gpioIoctlGPIO_ENABLE_PULLUP,
gpioIoctlGPIO_SETAS_INPUT,
gpioIoctlGPIO_SETAS_OUTPUT,
gpioIoctlGPIO_SETAS_GPIO,
gpioIoctlGPIO_SETAS_PERIPHERAL,
gpioIoctlGPIO_INTERRUPT_ASSERT_DISABLE,
gpioIoctlGPIO_INTERRUPT_ASSERT_ENABLE,
gpioIoctlGPIO_INTERRUPT_DISABLE,
gpioIoctlGPIO_INTERRUPT_ENABLE,
gpioIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_HIGH,
gpioIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_LOW,
gpioIoctlGPIO_CLEAR_INTERRUPT_PEND_REGISTER,
gpioIoctlGPIO_READ
}
#endif
};
const io_sGPIOInterface gpiopinInterfaceVT = {
gpiopinRead,
gpiopinWrite,
gpiopinClose,
{
gpiopinIoctlGPIO_SET,
gpiopinIoctlGPIO_CLEAR,
gpiopinIoctlGPIO_TOGGLE,
gpiopinIoctlGPIO_DISABLE_PULLUP,
gpiopinIoctlGPIO_ENABLE_PULLUP,
gpiopinIoctlGPIO_SETAS_INPUT,
gpiopinIoctlGPIO_SETAS_OUTPUT,
gpiopinIoctlGPIO_SETAS_GPIO,
gpiopinIoctlGPIO_SETAS_PERIPHERAL,
gpiopinIoctlGPIO_INTERRUPT_ASSERT_DISABLE,
gpiopinIoctlGPIO_INTERRUPT_ASSERT_ENABLE,
gpiopinIoctlGPIO_INTERRUPT_DISABLE,
gpiopinIoctlGPIO_INTERRUPT_ENABLE,
gpiopinIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_HIGH,
gpiopinIoctlGPIO_INTERRUPT_DETECTION_ACTIVE_LOW,
gpiopinIoctlGPIO_CLEAR_INTERRUPT_PEND_REGISTER,
gpiopinIoctlGPIO_READ
}
};
sGpioDevice pinPortAMap[] =
{
#if defined(BSP_DEVICE_NAME_GPIO_A)
{
(io_sInterface *)&gpiodrvIOInterfaceVT,
0, /* Base */
0xFFFF /* Mask */
},
#endif /* defined(BSP_DEVICE_NAME_GPIO_A) */
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x01 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x02 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x04 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x08 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x10 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x20 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x40 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x80 /* Mask */
}
};
sGpioDevice pinPortBMap[] =
{
#if defined(BSP_DEVICE_NAME_GPIO_B)
{
(io_sInterface *)&gpiodrvIOInterfaceVT,
0, /* Base */
0xFFFF /* Mask */
},
#endif /* defined(BSP_DEVICE_NAME_GPIO_B) */
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x01 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x02 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x04 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x08 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x10 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x20 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x40 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x80 /* Mask */
}
};
sGpioDevice pinPortCMap[] =
{
#if defined(BSP_DEVICE_NAME_GPIO_C)
{
(io_sInterface *)&gpiodrvIOInterfaceVT,
0, /* Base */
0xFFFF /* Mask */
},
#endif /* defined(BSP_DEVICE_NAME_GPIO_C) */
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x01 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x02 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x04 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x08 /* Mask */
}
};
sGpioDevice pinPortDMap[] =
{
#if defined(BSP_DEVICE_NAME_GPIO_D)
{
(io_sInterface *)&gpiodrvIOInterfaceVT,
0, /* Base */
0xFFFF /* Mask */
},
#endif /* defined(BSP_DEVICE_NAME_GPIO_D) */
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x01 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x02 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x04 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x08 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x10 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x20 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x40 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x80 /* Mask */
}
};
sGpioDevice pinPortEMap[] =
{
#if defined(BSP_DEVICE_NAME_GPIO_E)
{
(io_sInterface *)&gpiodrvIOInterfaceVT,
0, /* Base */
0xFFFF /* Mask */
},
#endif /* defined(BSP_DEVICE_NAME_GPIO_E) */
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x01 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x02 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x04 /* Mask */
},
{
(io_sInterface *)&gpiopinInterfaceVT,
0, /* Base */
0x08 /* Mask */
},
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