📄 const.c
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{
0, /* begin */
0, /* end */
ADCA_BUF_MASK, /* mask */
ADCA_BUF_OFFSET /* offset */
},
false /* is not initialized*/
};
struct sAdcDevice AdcBDeviceContext=
{
(io_sInterface *)&adc_IO, /* IO interface */
archoff_AdcB, /* ADC arch */
0, /* nUsedSamples */
0, /* ZeroCrossing mask */
0, /* HL | LL mask */
/* queue*/
{
0, /* begin */
0, /* end */
ADCB_BUF_MASK, /* mask */
ADCB_BUF_OFFSET /* offset */
},
false /* is not initialized*/
};
struct sAdcAnalogInput ANAContexts[8]; /* Analog Input descriptors */
struct sAdcAnalogInput ANBContexts[8]; /* Analog Input descriptors */
#endif /* INCLUDE_ADC*/
/*************************************************************************************/
#if defined(INCLUDE_SPI)
#if defined(INCLUDE_IO)
const struct io_sSPIInterface spi_blockIO ={spiBlockRead, spiBlockWrite, spiClose,SPI_IOCTL};
const struct io_sSPIInterface spi_nonblockIO ={spiNonBlockRead, spiNonBlockWrite, spiClose,SPI_IOCTL};
#else
const io_sInterface spi_blockIO ={noSpiBlockRead, noSpiBlockWrite, noSpiClose, noSpiIoctl};
const io_sInterface spi_nonblockIO ={noSpiNonBlockRead, noSpiNonBlockWrite, noSpiClose, noSpiIoctl};
#endif
struct sSPIDevice Spi0DeviceContext = {
(io_sInterface *)&spi_nonblockIO,
archoff_Spi0, /*SPI Arch */
{/* C3Buffer */
0, /* begin */
0, /* marker */
0, /* end */
SPI0_BUF_MASK, /* mask */
SPI0_BUF_OFFSET, /* buffer offset */
}
};
struct sSPIDevice Spi1DeviceContext = {
(io_sInterface *)&spi_nonblockIO,
archoff_Spi1, /*SPI Arch */
{/* C3Buffer */
0, /* begin */
0, /* marker */
0, /* end */
SPI1_BUF_MASK, /* mask */
SPI1_BUF_OFFSET /* buffer offset */
}
};
#endif /* INCLUDE_SPI */
#if defined(INCLUDE_DAC)
#if defined (INCLUDE_IO)
const struct io_sDACInterface dac_nonblockIO = {dacBlockRead , dacBlockWrite , dacClose , DAC_IOCTL};
const struct io_sDACInterface dac_blockIO = {dacNonBlockRead , dacNonBlockWrite , dacClose , DAC_IOCTL};
#else
const io_sInterface dac_blockIO = {noDacBlockRead, noDacBlockWrite, noDacClose, noDacIoctl};
const io_sInterface dac_nonblockIO = {noDacNonBlockRead, noDacNonBlockWrite, noDacClose, noDacIoctl};
#endif
struct sDACDevice DacADeviceContext =
{
(io_sInterface*)&dac_nonblockIO,
{DAC_A , DAC_CHANNEL_A, 0 , 0 , NULL}
};
struct sDACDevice DacBDeviceContext =
{
(io_sInterface*)&dac_nonblockIO,
{DAC_B , DAC_CHANNEL_B, 0 , 0 , NULL}
};
struct sDACDevice DacCDeviceContext =
{
(io_sInterface*)&dac_nonblockIO,
{DAC_C , DAC_CHANNEL_C, 0 , 0 , NULL}
};
struct sDACDevice DacDDeviceContext =
{
(io_sInterface*)&dac_nonblockIO,
{DAC_D , DAC_CHANNEL_D, 0 , 0 , NULL}
};
#endif /* INCLUDE_DAC */
/*****************************************************************************/
#if defined( INCLUDE_PWM )
#if defined(INCLUDE_IO)
#define PWM_IOCTLS { \
ioctlPWM_DEVICE_ENABLE, ioctlPWM_DEVICE_DISABLE, \
ioctlPWM_OUTPUT_PAD_ENABLE, ioctlPWM_OUTPUT_PAD_DISABLE,\
ioctlPWM_READ_FAULT_STATUS_REG, ioctlPWM_READ_COUNTER_REG, \
ioctlPWM_READ_CONTROL_REG, ioctlPWM_READ_PORT_REG, \
ioctlPWM_SET_CURRENT_SENSING, ioctlPWM_SET_LOAD_MODE, \
ioctlPWM_OUTPUT_SOFTWARE_CONTROL, ioctlPWM_OUTPUT_CONTROL, \
ioctlPWM_SET_SWAP, ioctlPWM_SET_CHANNEL_MASK \
}
const struct io_sPWMInterface pwm_IO ={noPwmBlockRead, noPwmBlockWrite, pwmClose, PWM_IOCTLS};
#else
const io_sInterface pwm_IO ={noPwmBlockRead, noPwmBlockWrite, noPwmBlockClose, noPwmIoctl};
#endif
/* clock = ms * IP_BUS_FREQ / 10^6 = ms * MICRO_IP_BUS_FREQUENCY */
const UWord32 MICRO_IP_BUS_FREQUENCY = (UWord32) BSP_OSCILLATOR_FREQ * PLL_MUL / 2 / 2 / 1000000;
struct sPwmDevice PwmADeviceContext =
{
(io_sInterface *)&pwm_IO,
archoff_PwmA,
{
/* volatile unsigned int begin = */ 0,
/* volatile unsigned int end = */ 0,
/* volatile unsigned int mask = */ PWMA_BUF_MASK,
/* volatile unsigned int bufferOffset = */ PWMA_BUF_OFFSET,
/* unsigned long reserved = */ 0
},
0
};
#if defined (BSP_DEVICE_NAME_PWM_B)
struct sPwmDevice PwmBDeviceContext =
{
(io_sInterface *)&pwm_IO,
archoff_PwmB,
{
/* volatile unsigned int begin = */ 0,
/* volatile unsigned int end = */ 0,
/* volatile unsigned int mask = */ PWMB_BUF_MASK,
/* volatile unsigned int bufferOffset = */ PWMB_BUF_OFFSET,
/* unsigned long reserved = */ 0
},
0
};
#endif
#if defined(INCLUDE_IO)
const struct io_sPWMInterface pwm_channel_blockIO ={noPwmBlockRead, pwmBlockWrite, pwmChannelClose, noPwmIoctl};
const struct io_sPWMInterface pwm_channel_nonblockIO ={noPwmNonBlockRead, pwmNonBlockWrite, pwmChannelClose, noPwmIoctl};
#else
const io_sInterface pwm_channel_blockIO ={noPwmBlockRead, noPwmBlockWrite, noPwmBlockClose, noPwmIoctl};
const io_sInterface pwm_channel_nonblockIO ={noPwmNonBlockRead, noPwmNonBlockWrite, noPwmBlockClose, noPwmIoctl};
#endif
struct sPwmChannel PwmChannel[] =
{
#ifdef BSP_DEVICE_NAME_PWM_A
{ NULL, &PwmADeviceContext, 1, 1, 0, 0x0001},
{ NULL, &PwmADeviceContext, 1, 2, 0, 0x0002},
{ NULL, &PwmADeviceContext, 1, 3, 0, 0x0004},
{ NULL, &PwmADeviceContext, 1, 4, 0, 0x0008},
{ NULL, &PwmADeviceContext, 1, 5, 0, 0x0010},
{ NULL, &PwmADeviceContext, 1, 6, 0, 0x0020},
{ NULL, &PwmADeviceContext, 2, 1, 0, 0x0003},
{ NULL, &PwmADeviceContext, 2, 3, 0, 0x000C},
{ NULL, &PwmADeviceContext, 2, 5, 0, 0x0030},
{ NULL, &PwmADeviceContext, 3, 1, 0, 0x0007},
{ NULL, &PwmADeviceContext, 3, 4, 0, 0x0038},
{ NULL, &PwmADeviceContext, 6, 1, 0, 0x003F},
#endif
#ifdef BSP_DEVICE_NAME_PWM_B
{ NULL, &PwmBDeviceContext, 1, 1, 0, 0x0001},
{ NULL, &PwmBDeviceContext, 1, 2, 0, 0x0002},
{ NULL, &PwmBDeviceContext, 1, 3, 0, 0x0004},
{ NULL, &PwmBDeviceContext, 1, 4, 0, 0x0008},
{ NULL, &PwmBDeviceContext, 1, 5, 0, 0x0000},
{ NULL, &PwmBDeviceContext, 1, 6, 0, 0x0000},
{ NULL, &PwmBDeviceContext, 2, 1, 0, 0x0003},
{ NULL, &PwmBDeviceContext, 2, 3, 0, 0x000C},
{ NULL, &PwmBDeviceContext, 2, 5, 0, 0x0030},
{ NULL, &PwmBDeviceContext, 3, 1, 0, 0x0007},
{ NULL, &PwmBDeviceContext, 3, 4, 0, 0x0038},
{ NULL, &PwmBDeviceContext, 6, 1, 0, 0x003F},
#endif
{ NULL, NULL, 0, 0, 0, 0}
};
#endif /* INCLUDE_PWM */
/*****************************************************************************/
#if defined( INCLUDE_MSCAN )
static UWord16 readBuf[CAN_RX_BUFFER_SIZE(CAN_RECEIVE_ID_QUEUE_SIZE) * CAN_MAX_RECEIVE_ID];
static can_sWriteBuffer writeBuf[CAN_MAX_TRANSMIT_ID];
const io_sMSCANInterface canInterfaceVT = {
canRead,
canWrite,
canClose,
{ ioctlCAN_GET_STATUS,ioctlCANID_GET_STATUS,
ioctlCAN_RESET,ioctlCAN_SET_SLEEP,ioctlCAN_SET_WAKEUP
} /* Ioctl */
};
const can_pRawCallBack CANRcvPrepare = /* RAW CallBack pointer */
#if defined(CAN_RAW_CALLBACK)
(can_pRawCallBack)CAN_RAW_CALLBACK;
#else
#if defined(CAN_RECEIVE_HANDLER_USES_PRAGMA_INTERRUPT)
NULL;
#else
(can_pRawCallBack)CANStdRcvPrepare;
#endif
#endif /* ifndef CAN_RAW_CALLBACK */
const can_sInitialState canInitialState = {
"CAN",
(can_sReadBuffer *)&readBuf[0],
(can_sReadBuffer *)&readBuf[CAN_RX_BUFFER_SIZE(CAN_RECEIVE_ID_QUEUE_SIZE) * CAN_MAX_RECEIVE_ID ],
CAN_RX_BUFFER_SIZE(CAN_RECEIVE_ID_QUEUE_SIZE),
(can_sWriteBuffer *)&writeBuf[0],
(can_sWriteBuffer *)&writeBuf[CAN_MAX_TRANSMIT_ID],
#if defined(CAN_RAW_CALLBACK)
(can_pRawCallBack)CAN_RAW_CALLBACK,
#else
NULL,
#endif /* ifndef CAN_RAW_CALLBACK */
CAN_STOP_IN_WAIT_MODE << 5,
CANCANE | (CAN_LOOP_BACK << 2) | (CAN_WAKE_UP_MODE << 1) | CAN_CLOCK_SOURCE,
((CAN_SYNCH_JUMP_WIDTH - 1) << 6) | ( CAN_PRESCALER - 1 ),
(CAN_SAMPLING << 7) | ( (CAN_TIME_SEGMENT2 - 1 ) << 4 ) | ( CAN_TIME_SEGMENT1 - 1 ),
CAN_CUSTOM_FILTER_CODE,
CAN_CUSTOM_FILTER_MASK,
CAN_ROUND2UP( CAN_RECEIVE_ID_QUEUE_SIZE ) - 1,
CAN_TX_ERROR_ASSERT == CAN_ASSERT_WARNING ? CANTWRNIE | CANTERRIF | CANBOFFIE
: CAN_TX_ERROR_ASSERT == CAN_ASSERT_ERROR ? CANTERRIF | CANBOFFIE
: CANBOFFIE
};
#endif /* INCLUDE_MSCAN */
/*****************************************************************************/
#if defined( INCLUDE_FLEXCAN )
#if defined(INCLUDE_IO)
const io_sFLEXCANInterface canInterfaceVT = {
flexcanRead,
flexcanWrite,
flexcanClose,
{ ioctlCAN_GET_STATUS, ioctlCANID_GET_STATUS,
ioctlCAN_RESET, ioctlCAN_SET_SLEEP, ioctlCAN_SET_WAKEUP,
}, /* Ioctl */
};
#else /* INCLUDE_IO */
const io_sFLEXCANInterface canInterfaceVT = {
no_read,
no_write,
no_close,
{ no_ioctl, no_ioctl,
no_ioctl, no_ioctl, no_ioctl
}, /* Ioctl */
};
#endif /* INCLUDE_IO */
const can_pRawCallBack CANRcvPrepare = /* RAW CallBack pointer */
#if defined(CAN_RAW_CALLBACK)
CAN_RAW_CALLBACK;
#else
NULL;
#endif /* ifndef CAN_RAW_CALLBACK */
const can_sInitialState canInitialState = {
3,
#if defined(CAN_RAW_CALLBACK)
CAN_RAW_CALLBACK,
#else
NULL,
#endif /* ifndef CAN_RAW_CALLBACK */
/* FCMCR = */ 0x5000
| ( CAN_WAKE_UP_MODE << 6 ),
/* FCCTL0 = */ 0
| ( CAN_SAMPLING << 7)
| ( CAN_LOOP_BACK << 6)
| ( CAN_PROP_SEGMENT - 1) ,
/* FCCTL1 = */ 0
| (( CAN_PRESCALER - 1 ) << 8)
| (( CAN_SYNCH_JUMP_WIDTH - 1) << 6)
| (( CAN_PHASE_SEGMENT1 - 1 ) << 3 )
| ( CAN_PHASE_SEGMENT2 - 1 )
};
const unsigned int FlexCANFlags = 0
#if defined( CAN20B )
| O_CAN_2B
#endif
#if CAN_LOOP_BACK == 1
| O_LOOP_BACK
#endif /* defined( CAN_LOOP_BACK ) */
;
#endif /* INCLUDE_FLEXCAN */
/*****************************************************************************/
#if defined( INCLUDE_COP )
const unsigned int copPeriodMicroSeconds = ((COP_PRESCALER * 1000000UL) / BSP_OSCILLATOR_FREQ);
const struct io_sCOPInterface COPInterfaceVT = {
NULL,
NULL,
copClose,
{
ioctlCOP_RELOAD,
ioctlCOP_GET_RESET_STATUS,
ioctlCOP_CLR_RESET_STATUS
} /* Ioctl */
};
#endif
/*****************************************************************************/
#if defined( INCLUDE_FILEIO )
const struct io_sFileIOInterface fileioInterfaceVT = {
fileioRead,
fileioWrite,
fileioClose,
{ioctlFILEIO} /* Ioctl */
};
#ifndef FILEIOFILESLIMIT
#define FILEIOFILESLIMIT 2
#endif
#if FILEIOFILESLIMIT > 10
#error No more then 10 files can be opened
#endif
const int fileioFilesLimit = FILEIOFILESLIMIT;
struct fileio_Handle fileDriver[FILEIOFILESLIMIT];
#endif
/*****************************************************************************/
#if defined( INCLUDE_SCI )
#if defined(INCLUDE_IO)
const struct io_sSCIInterface scidrvIOBlockInterfaceVT =
{
sciBlockRead, sciBlockWrite, sciClose, SCI_IOCTLs
};
const struct io_sSCIInterface scidrvIONonBlockInterfaceVT =
{
sciNonBlockRead, sciNonBlockWrite,sciClose, SCI_IOCTLs
};
#else /* INCLUDE_IO */
const io_sInterface scidrvIOBlockInterfaceVT =
{
noSciBlockRead, noSciBlockWrite, noSciClose, noSciIoctl
};
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