arch.c

56f8300E系列dsp的BOOTloader

/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
* $Element: /project/dsp568_sdk/sdk/src/dsp56838evm/nos/sys/arch.c $ 
* $Author: saa $ 
* $Revision: /main/2 $ 
* $VOB: /project/dsp568_sdk $ 
* $OS: solaris $ 
*
* Description:  Startup and standard dispatcher
*
* Notes:          
*
******************************************************************************/

#include "port.h"
#include "bsp.h"


#include "arch.h"
#include "arch_off.h"
#include "periph.h"

#define INCLUDE_PLL
#include "pll.h"

/* Internal Oscillator Calibration */
#define PLL_CALIBRATION_ADDRESS 		0xF41B 
#define PLL_CALIBRATION_ERASED 			0xffff
UWord16 plldrvCalibrate(void);

#include "supconfig.h"
#include "config.h"

                                                     

extern void * archStartDelayAddress;
//extern void archStart(void);      /* Defined in linker.cmd file */
extern int  * _StackAddr;           /* Defined in linker.cmd file */
extern void * _Xbss_begin_addr;
extern void * _Xbss_length;


extern void * _Xdata_ROMtoRAM_length;      
extern void * _Xdata_begin_addr_in_RAM;    
extern void * _Xdata_begin_addr_in_ROM;   
extern void * _Pcode_end_addr_in_ROM; 

extern UWord16  RegState[];
extern arch_PeriphRegState peripheralReg[archoff_registers_num];

extern void configFinalize();
extern void configInitialize();
void configInterruptVector(void);
void archPreConfig(void);

void archStart()
{
    extern void main(void);
 	int i, j, k;

    enum tmpsemi { 
        semiopt0 = 0x07c0 | (PMEM_WAIT_STATE & 0x001F),
        semiopt1 = 0x03a0 | (XMEM_WAIT_STATE & 0x001F),
        semiopt2 = 0x05a0 | (XMEM_WAIT_STATE & 0x001F),
        semi_CSBAR_0 = 0x0008,//START_ADDRESS_P_EXT_RAM(_128KWords) | SIZE_P_EXT_RAM(_128KWords),
        semi_CSBAR_1 = 0x0005,
        semi_CSBAR_2 = 0x0005
    };
 
    
#if 0
    asm( bfset   #0x8000, OMR );        /* Set Nested DO Loop Bit */
#endif /* 0 */
    asm( moveu.w    #0xFFFF, M01 );     /* Set the m register to linear addressing */
    asm( bfclr   #0x01B0, OMR );        /* Set  CM(32-bit) XP(harvard architecture), 
                                        /* R(Convergent rounding),  SA(Saturation disabled) */
    asm( moveu.w    hws, la );             /* Clear the hardware stack */
    asm( moveu.w    hws, la );

    asm(bfset #0x0300, SR);             /* disable interrupts */                    
    
#if !defined( EXCLUDE_EXT_MEM )
    
    /*** EXT memory inintialization ***/
    asm( bfset  #1, X:(BSP_PERIPH_BASE + archoff_PortD_PeripheralReg) );
    asm( move.w #semiopt0, X:(BSP_PERIPH_BASE + archoff_Semi_OptionReg0) );
    asm( move.w #semi_CSBAR_0, X:(BSP_PERIPH_BASE + archoff_Semi_BaseAddressReg0) );
    asm( move.w #semiopt1, X:(BSP_PERIPH_BASE + archoff_Semi_OptionReg1) );
    asm( move.w #semi_CSBAR_1, X:(BSP_PERIPH_BASE + archoff_Semi_BaseAddressReg1) );
    asm( move.w #semiopt2, X:(BSP_PERIPH_BASE + archoff_Semi_OptionReg2) );
    asm( move.w #semi_CSBAR_2, X:(BSP_PERIPH_BASE + archoff_Semi_BaseAddressReg2) );

#endif /* !defined( EXCLUDE_EXT_MEM ) */

/***  stack and data section ***/

    asm( moveu.w #_StackAddr, SP );     /* assign stack address */
#if 1 /* check in linker file */
    asm( alignsp );                     /* Set stack pointer to known location */
#endif /* 1 */
                
    asm( moveu.w  #_Xbss_length, N );      /* 64K bss  */
    asm( move.l  #>>_Xbss_begin_addr, R2 ); /* Clear internal ram to initialize all */

    asm( clr.w X0 );                    /* loop to initialize bss section */
    asm( rep   N );
    asm( move.w  X0, x:(R2)+ );
#if 0
    asm( moveu.w  #_Xdata_ROMtoRAM_length, N );      /* 64K RAM size */
    asm( move.l  #>>_Xdata_begin_addr_in_RAM, R2 );    
    asm( move.l  #>>_Pcode_end_addr_in_ROM, R3 );    

    
    asm( do  N, copy_data );             /* loop to copy data section */
    asm( move.w  P:(R3)+, X0  );            
    asm( nop );
    asm( nop );
    asm( move.w  X0, X:(R2)+ );
asm(copy_data:);   /*  end loop */

#endif

#if !defined( EXCLUDE_PLL )
#if defined (DSP56832XEVM)
	/* Calibrate the internal oscillator to 8MHz */
	plldrvCalibrate();/* System clock initialization */
		
    /* System clock initialization */
//  setRegBit(PLLCR, PLLPD);             /* Disable PLL */
//  setReg(PLLDB, 29);                   /* Set the clock prescalers */
//  setRegBit(PLLCR, LCKON);             /* Enable lock detector */
//  clrRegBit(PLLCR, PLLPD);             /* Enable PLL */
//  while(!getRegBit(PLLSR, LCK0)){}     /* Wait for PLL lock */

//  setRegBitGroup(PLLCR, ZSRC, 2);      /* Select clock source from postscaler */
//  setRegBit(OSCTL, CLK_MODE);          /* Select an internal oscillator mode */
//  clrRegBit(PLLCR, PRECS);             /* Select an internal clock source for the DSP core */
//  setRegBit(OSCTL, ROPD);              /* External oscillator power-down */

#endif
    /* set lock detector on and choose core clock */
    asm( move.w	#PLL_LOCK_DETECTOR | PLL_ZCLOCK_PRESCALER, X:(BSP_PERIPH_BASE + archoff_Pll_ControlReg )   );

    /* if LORTP is zero we have to save old value (prevent generate of lock interrupted) */
    asm( bfclr #0x0FFF, X:(BSP_PERIPH_BASE + archoff_Pll_DivideReg )   );
    asm( bfset #PLL_DIVIDE_BY_REG, X:(BSP_PERIPH_BASE + archoff_Pll_DivideReg )   );

    asm( move.w  #0x4000, X0 );            /* set x0 with timeout value */
    
    asm( wait_pll: );
    asm( dec.w X0 );
    asm( brset #PLL_STATUS_LOCK_0, X:(BSP_PERIPH_BASE + archoff_Pll_StatusReg ), end_wait  );
    asm( cmp.w #0, X0 );
    asm( bne wait_pll );

   /* PLL did not lock, but proceed anyway */
    asm( end_wait: );
    asm( move.w	#PLL_CONTROL_REG, X:(BSP_PERIPH_BASE + archoff_Pll_ControlReg )   );

#endif /* !defined( EXCLUDE_PLL ) */
    
#if 0 

 /*Keep the power on reset state for peripheral registers */   
 	
 	k = 0;
 	for (i = 0; i < archoff_registers_num; i++)
 	{
 		for (j = 0; j <  peripheralReg[i].length; j ++)
 		{
 			RegState[k] = periphMemRead( (volatile UWord16 *) (peripheralReg[i].StartAddress + j));
 			k++;
 		}
			
 	}; 
 /**/
 
#endif  
    asm( jsr configInitialize );        /* initialize configurable hardware */

    asm(bfclr #0x0300,SR) ;         /* enable interrupt */

    asm( jsr main  );               /* call the application */
 
    asm( jsr configFinalize );      /* Flush output, handle end of program */


    asm( forever: );
    asm( debughlt );
    asm( bra   forever  );           /* Loop forever if return from user application */

}


void Dispatcher(void);

asm void Dispatcher()
{
    move.l  A2,x:(SP)+ 
    move.l  B2,x:(SP)+
    move.l  X0,x:(SP)+
    move.l  Y,x:(SP)+
    move.l  N3,x:(SP)+
    move.l  M01,x:(SP)+
    move.l  OMR,x:(SP)+

    move.l  C2,x:(SP)+
    move.l  D2,x:(SP)+
    move.l  A10,x:(SP)+
    move.l  B10,x:(SP)+
    move.l  N,x:(SP)+
    move.l  R1,x:(SP)+
    move.l  R2,x:(SP)+
    move.l  R3,x:(SP)+

    /* save hardware loop stack and registers */
  
    move.l  la,x:(SP)+
    move.l  la2,x:(SP)+
    move.l  lc2,x:(SP)+
    move.l  lc,x:(SP)+
    move.l  hws,x:(SP)+
    move.l  hws,x:(SP)+

    //; set consistent state for critical registers
    bfclr   #$0130,OMR  //; convergent rounding, no saturation mode, 36-bit compares

    move.l  R4,x:(SP)   //; save last register in context. Moved here to eliminate nop.

    moveu.w #0xFFFF,m01  //; linear addressing       

    jsr (R0)
    
FDispatchRestore:

    move.l  x:(SP)-,R4

    //; restore hardware stack
    move.w  hws,A   // ; clear HWS to ensure reload
    move.w  hws,A
    move.l  x:(SP)-,hws
    move.l  x:(SP)-,hws
    
    //; restore all saved registers
    move.l  x:(SP)-,lc
    move.l  x:(SP)-,lc2
    move.l  x:(SP)-,la2
    move.l  x:(SP)-,la

    move.l  x:(SP)-,R3
    move.l  x:(SP)-,R2
    move.l  x:(SP)-,R1
    move.l  x:(SP)-,N
    move.l  x:(SP)-,B
    move.l  x:(SP)-,A

    move.l  x:(SP)-,D2
    move.l  x:(SP)-,C2
    move.l  x:(SP)-,OMR 
    move.l  x:(SP)-,M01
    move.l  x:(SP)-,N3
    move.l  x:(SP)-,Y
    move.l  x:(SP)-,X0
    move.l  x:(SP)-,B2
    move.l  x:(SP)-,A2
    move.l  x:(SP)-,R0   /* R0 saved in prolog procedure */
    move.l  x:(SP)-,SP
    nop        
    nop
    
    rti
}
/*******************************************************************************
*
* Module: plldrvCalibrate()
*
* Description: 
*     Set the internal oscillator control register (IOSCTL) to the factory 
*     calibration value. This value is calibrated to 8MHz at room temperature
*     at the factory. If the value is invalid (0xFFFF), the IOSCTL will not 
*     be changed.
*
* Returns: Factory Calibration value.
*
* Arguments: None.
*
* Range Issues: None.
*
* Special Issues:
*     The calibration value is stored at the end of the Data Flash information
*     block (0xF41B). This address is RESERVED but may be overwritten by the user  
*     to force a different calibration value.
*
*******************************************************************************/
UWord16 plldrvCalibrate(void)
{
	UWord16 trimval;

	/* Write calibration value if programmed */
	trimval = *(UWord16 *) PLL_CALIBRATION_ADDRESS;
	
	if (trimval != PLL_CALIBRATION_ERASED)
	{   
		trimval = trimval & 0x00FF;
		trimval = trimval | periphMemRead(&ArchIO.Pll.OscControlReg);
		periphMemWrite(trimval, &ArchIO.Pll.OscControlReg);
   	}

   	return (trimval);
}