pll.h
来自「56f8300E系列dsp的BOOTloader」· C头文件 代码 · 共 91 行
H
91 行
/*******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2002 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
* $Element: /project/dsp568_sdk/sdk/src/dsp56838evm/nos/include/pll.h $ * $Author: saa $ * $Revision: /main/2 $ * $VOB: /project/dsp568_sdk $ * $OS: solaris $ *
* Description: Header file for PLL
*
* Notes:
*
******************************************************************************/
#ifndef __PLL_H
#define __PLL_H
#include "port.h"
#ifdef __cplusplus
extern "C" {
#endif
/* PLL control register flags, see OCCS documentation */
#define PLL_INT1_ENABLE_ANY_EDGE 0xC000
#define PLL_INT1_ENABLE_FALLING_EDGE 0x8000
#define PLL_INT1_ENABLE_RISING_EDGE 0x4000
#define PLL_INT0_ENABLE_ANY_EDGE 0x3000
#define PLL_INT0_ENABLE_FALLING_EDGE 0x2000
#define PLL_INT0_ENABLE_RISING_EDGE 0x1000
#define PLL_LOSS_OF_CLOCK_INT 0x0800
#define PLL_LOCK_DETECTOR 0x0080
#define PLL_CHARGE_PUMP 0x0040
#define PLL_PWRDONW 0x0010
#define PLL_ZCLOCK_PRESCALER 0x0001
#define PLL_ZCLOCK_POSTSCALER 0x0002
/* PLL divide-by register flag */
#define PLL_CLOCK_OUT_DIVIDE_BY_1 0x0000
#define PLL_CLOCK_OUT_DIVIDE_BY_2 0x0400
#define PLL_CLOCK_OUT_DIVIDE_BY_4 0x0800
#define PLL_CLOCK_OUT_DIVIDE_BY_8 0x0C00
#define PLL_CLOCK_IN_DIVIDE_BY_1 0x0000
#define PLL_CLOCK_IN_DIVIDE_BY_2 0x0100
#define PLL_CLOCK_IN_DIVIDE_BY_4 0x0200
#define PLL_CLOCK_IN_DIVIDE_BY_8 0x0300
/* PLL status register flags */
#define PLL_STATUS_LOCK_LOST_INT1 0x8000
#define PLL_STATUS_LOCK_LOST_INT0 0x4000
#define PLL_STATUS_CLOCK_LOST 0x2000
#define PLL_STATUS_LOCK_1 0x0040
#define PLL_STATUS_LOCK_0 0x0020
#define PLL_STATUS_POWERED_DOWN 0x0010
#define PLL_STATUS_ZCLOCK_PRESCALER 0x0001
#define PLL_STATUS_ZCLOCK_POSTSCALER 0x0002
/* PLL shutdown register */
/* SDK initialization routine */
void PLLInitialize(UWord16 ControlReg, UWord16 DivideReg);
void InstallPll(void); /* configurable function */
#ifdef __cplusplus
}
#endif
#endif
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