📄 mt352.h
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#define CLOCK 0x02 /* b2 SCL*/
#define DATA 0x01 /* b1 SDA*/
#define ENABLE 0x20 /* b5 SLEEP*/
#define EVENT 0x10 /* b4 EVENT */
#endif
/* addresses of registers to control M16C parallel I/O port number 5*/
#define PORT_DDR *(u8 *) 0x03EF /*I/O Port direction control register*/
#define PORT_READ *(volatile u8 *) 0x03ED /*I/O Port Read address*/
#define PORT_WRITE *(u8*) 0x03ED /*I/O Port Write address*/
/*
Uhen system is in lock or idle, the MT352 state is checked this often
the rs timer depends on counting this, so use values 500, 250,125
*/
#define TNIM_REFRESH_TIME 100
/*#defines for tuner settings in StnimTunerInfo*/
#define TUNER_IF1_OUTPUT 0x01 /*output to MT352 is 36 or 44 MHz, not 4.57*/
#define TUNER_LO_INJECTION 0x02 /*1st LO is below RF input frequency*/
#define TUNER_SPECTRAL_INV 0x04 /*additional spectral inversion required */
/********************* ALPS TDLB7X900A 4.57MHz output tuner *******************/
/***************** SEM TECC2349PG39L 36MHz ouput tuner ************************/
#define SEM_TECC2349PG_TABLE \
50, 0xB401,16667, /*control bytes above 50MHz RF */ \
150,0xBC01,16667, /*control bytes above 150MHz RF */ \
175,0xB402,16667, /*control bytes above 175MHz RF */ \
400,0xBC02,16667, /*control bytes above 400MHz RF */ \
470,0xBC08,16667, /*control bytes above 470MHz RF */ \
730,0xF408,16667 /*control bytes above 730MHz RF */
#define SEM_TECC2349PG_INFO \
0xC2, /* address*/ \
6, /* table count*/ \
TUNER_IF1_OUTPUT, /* settings*/ \
36167, /* synth IF frequency kHz*/ \
{0x10,0x23,0x00,0xFF,0xFF,0x00,0xFF,0x00,0x40,0x40},\
/* AGC control bytes */ \
0x00, /* 6MHz SAW*/ \
0x00, /* 7MHz SAW*/ \
0x00 /* 8MHz SAW*/
#define THOM_DTT7592_TABLE \
177, 0xB402,16667, /*control bytes above 177MHz RF */ \
470,0xBC08,16667, /*control bytes above 470MHz RF */ \
699,0xF408,16667, /*control bytes above 699MHz RF */ \
799,0xFC08,16667, /*control bytes above 799MHz RF */
#define THOM_DTT7592_INFO \
0xC2, /* address*/ \
6, /* table count*/ \
TUNER_IF1_OUTPUT, /* settings*/ \
36000, /* synth IF frequency kHz*/ \
{0x30,0x20,0x00,0xFF,0xFF,0x00,0xFF,0x00,0x40,0x40},\
/* AGC control bytes */ \
0x10, /* 6MHz SAW*/ \
0x10, /* 7MHz SAW*/ \
0x00 /* 8MHz SAW*/
#define SEM_TDTC8250_INFO \
0xC2, /* address*/ \
6, /* table count*/ \
TUNER_IF1_OUTPUT, /* settings*/ \
36167, /* synth IF frequency kHz*/ \
{0x15,0xA0,0x00,0xFF,0xFF,0x00,0xFF,0x00,0x40,0x40},\
/* AGC control bytes */ \
0x00, /* 6MHz SAW*/ \
0x00, /* 7MHz SAW*/ \
0x00 /* 8MHz SAW*/
#define COMTECK_DVBT_35208_INFO \
0xC0, /* address*/ \
6, /* table count*/ \
TUNER_IF1_OUTPUT, /* settings*/ \
36167, /* synth IF frequency kHz*/ \
{0x25,0x22,0x00,0xFF,0xFF,0x00,0xFF,0x00,0x40,0x40},\
/* AGC control bytes */ \
0x00, /* 6MHz SAW*/ \
0x00, /* 7MHz SAW*/ \
0x00 /* 8MHz SAW*/
#define SEM_DNOS204_INFO \
0xC2, /* address*/ \
6, /* table count*/ \
TUNER_IF1_OUTPUT, /* settings*/ \
36167, /* synth IF frequency kHz*/ \
{0x10,0x20/*0x23*/,0x00,0xFF,0xFF,0x00,0xFF,0x00,0x40,0x40},\
/* AGC control bytes */ \
0x00, /* 6MHz SAW*/ \
0x00, /* 7MHz SAW*/ \
0x00 /* 8MHz SAW*/
////////////////////////////////////////////////////////////////////////////////
/******************************** PARTSNIC_TNIM ******************************/
#define PARTSNIC_TNIM_TABLE \
213, 0xB402,16667, /*control bytes above 213MHz RF */ \
510,0xB608,16667, /*control bytes above 264 MHz RF */ \
735,0xF408,16667, /*control bytes above 175MHz RF */ \
835,0xF608,16667, /*control bytes above 400MHz RF */ \
#define PARTSNIC_TNIM_INFO \
0xC2, /* address*/ \
6, /* table count*/ \
TUNER_IF1_OUTPUT, /* settings*/ \
36167, /* synth IF frequency kHz*/ \
{0x10,0x23,0x00,0xFF,0xFF,0x00,0xFF,0x00,0x40,0x40}, \
/* AGC control bytes */ \
0x00, /* 6MHz SAW*/ \
0x00, /* 7MHz SAW*/ \
0x00 /* 8MHz SAW*/
#if defined(SEM_TECC2349PG)
#define TUNER_TABLE SEM_TECC2349PG_TABLE
#define TUNER_INFO SEM_TECC2349PG_INFO
// #pragma message("Default build is for SEM_TECC2349PG ouput tuner")
#elif defined(THOM_DTT7592)
#define TUNER_TABLE THOM_DTT7592_TABLE
#define TUNER_INFO THOM_DTT7592_INFO
#elif defined(SEM_TDTC8250)
#define TUNER_TABLE SEM_TECC2349PG_TABLE
#define TUNER_INFO SEM_TDTC8250_INFO
// #pragma message("Default build is for SEM_TDTC8250 ouput tuner")
#elif defined(COMTECK_DVBT_3528)
#define TUNER_TABLE SEM_TECC2349PG_TABLE
#define TUNER_INFO COMTECK_DVBT_35208_INFO
// #pragma message("Default build is for COMTECK_DVBT_3528 ouput tuner")
#elif defined(SEM_DNOS204)
#define TUNER_TABLE SEM_TECC2349PG_TABLE
#define TUNER_INFO SEM_DNOS204_INFO
// #pragma message("Default build is for SEM_DNOS204 ouput tuner")
#elif defined(PARTSNIC_TNIM)
#define TUNER_TABLE PARTSNIC_TNIM_TABLE
#define TUNER_INFO PARTSNIC_TNIM_INFO
// #pragma message("Default build is for PDNTF09D ouput tuner")
#else
#pragma message("No Default tuner has been selected")
#error "Not defined the tuner type."
#endif
/***********************************************************************************************************\
* EXTERNAL FUNCTIONS REQUIRED *
\***********************************************************************************************************/
/* 2 wire bus: Read byCount bytes from register number byReg in device at address byID into buffer at pBuffer*/
typedef bool8 (*PFRegisterRead)(u8 byID,u8 byReg, u8 *pBuffer,u8 byCount);
/* 2 wire bus: Write byCount bytes from buffer at pBuffer in register number byReg in device at address byID */
typedef bool8 (*PFRegisterWrite)(u8 byID,u8 byReg, u8 *pBuffer,u8 byCount);
/*
If hardware exists that switches the power supply to the Demodulator circuitry, this function turns it on or off as required.
byEnableNo allows selection of particular Snim, when more than 1 exist (this is the value STnimControl.enableNo)
If no power switching is required, this value must be NULL
*/
typedef bool8 (*PFEnable)(bool8 bWantOn, u8 byEnableNo);
/* channel structure*/
typedef struct STnimChannel
{
u8 Number; /* channel number 0 to 127 */
s8 Offset; /* offset +/- 1*/
}STnimChannel,*PSCHANNEL;
typedef struct STnimAuxChannelInfo
{
u8 ucValid; /* contains TPS and CellID valid bits*/
u16 wTPS; /* TPS info*/
u16 wCellID;/*Cell ID*/
}STnimAuxChannelInfo,* PSAUXINFO;
/***********************************************************************************************************\
* STRUCTURE DEFINITIONS *
\***********************************************************************************************************/
/* structure to read AGC*/
typedef struct STnimAGC
{
u16 wIFpri;
u16 wRFsec;
u16 wTotal;
}STnimAGC,*PSAGC;
/* tuner frequency dependent information */
typedef struct STnimTunerTable
{
u16 FreqMHz; /* RF input frequency above which the following control word applies */
u16 Control; /* 16 bit synth control(charge pump, div ratio, band switch etc)*/
u16 FcompkHzx100; /* comparison frequency(step size)*/
}STnimTunerTable, * PSTUNERTABLE;
/*Scan information*/
typedef struct STnimScanInfo
{
u8 ChanFirst;
u8 ChanLast;
u8 Options;
}STnimScanInfo,* PSSCANINFO;
/* Tuner control settings*/
typedef struct STnimTunerInfo
{
u8 Address; /* bus address of tuner*/
u8 TableCount; /* number of entries in TunerTable*/
u8 Settings; /* misc settings */
u16 IF1kHz; /* tuner IF1 kHz for synth calcs (e.g. 36167)*/
u8 AGC[10]; /* AGC control bytes (MT352 reg 0x67 to 0x70 inc*/
u16 Control6MHz; /* extra Control bits to set for 6MHz*/
u16 Control7MHz; /* extra Control bits to set for 7MHz*/
u16 Control8MHz; /* extra Control bits to set for 8MHz*/
}STnimTunerInfo, * PSTUNERINFO;
/******************************************************************************\
* INITIALISATION MACROS *
* NB these macros are not used within the driver set, they are provided for *
* convenience only. It is recommended that you copy these to your own files *
* and modify if required. *
* *
\******************************************************************************/
/*
STnimControl general configuration. For use with reference design, tuner table
is selected by build defines above
*/
#define STNIMCONTROL_DEFAULT(t,READ_REG_2W,WRITE_REG_2W,SLAVE_ACCESS_2W,ENABLE,MILLISECONDS)\
{ \
\
struct STnimTunerTable TnimTunerTable; \
extern struct STnimTunerInfo TnimTunerInfo; \
u16 x; \
u8 *p=(u8*) &t; \
for (x=0;x<sizeof(STnimControl);x++) \
{*p=0; p++;} \
t.DeviceID = 30; \
t.NoAutoRSUBC = 1; \
t.NoMDOswap = 1; \
t.pfRegisterRead =(PFRegisterRead)READ_REG_2W; \
t.pfRegisterWrite =(PFRegisterWrite)WRITE_REG_2W; \
t.pfEnable= (PFEnable)ENABLE; \
t.pMilliSeconds= &MILLISECONDS; \
t.psTunerInfo = &TnimTunerInfo; \
t.psTunerTable = &TnimTunerTable; \
}
/*
Main control structure for Snim module. Each Snim module in a system requires its own structure
which contains internal state information. Synthesiser tables, millisecond clock and bus functions
may be common to all Snims
Deafault values are mostly zero (use STNIMCONTROL_DEFAULT macro to initailise as required
*/
typedef struct STnimControl
{
u8 DeviceID; /* 2 wire bus address of Snim default 0x28*/
u8 EnableNo; /* select enable (sleep) control line*/
/* Configuration default is all bits 0, listed first*/
BitsT Xtal:2; /* Crystal 0= 20.48: 1= 19.5, 2= 27, 3= 4MHz */
BitsT AdcPll:1; /* Clock ADC from Xtal(if poss):1 = clock ADC from pll*/
BitsT MpegOff:1; /* MPEG enabled: 1 = leave MPEG tristated at power up */
BitsT NoTEI:1; /* TEI in MPRG: 1= no error indicator in mpeg stream*/
BitsT NoMDOswap:1; /* MPEG pinout reversed: 1 =not reversed*/
BitsT NoBKERRinvert:1; /* Invert BKerr: 1= do not*/
BitsT MPEGserial:1; /* Parallel MPEG: 1= serial*/
BitsT NoMPEGgap12:1; /* 12.5 bytes packet gap:1 = not*/
BitsT NoMPEGClkInv:1; /* MPEGClock inverted: 1 = no inversion *///XFDONG
BitsT MPEGclkinEn:1; /* Normal: 1= use ext MPEG clock at start up*/
BitsT NoAutoRSUBC:1; /* disable automatic RSUBC timer*/
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