mt352.c

PHILIPS1316 tuner 驱动软件用于PHILIPS TDM1316 DVB-T tuner。经过实际测试。

	TunerByte4=0x86;//DNOS204ZH101A
//	TunerByte4=0x84;//DNOS204ZH102A
	/* ChargePump Setting version 1*/
	if(dwTunerFreq < 546001)
	{/*3 --> 125uA (extended)*/ //CP=1;
		TunerByte4=TunerByte4 | 0x38;
	}
	else if(dwTunerFreq < 834001)
	{/*4 --> 250uA (extended)*/ //CP=2;
		TunerByte4=TunerByte4 | 0x70;
	}
	else if(dwTunerFreq < 884001)
	{/*5 --> 650uA (extended)*/ //CP=3;
		TunerByte4=TunerByte4 | 0x78;
	}
	else
	{
	printf("Error Input Centerfreq");
	}

	if(dwTunerFreq < 173251)
	{
		TunerByte5 = 0x01;
	}
	else if(dwTunerFreq < 470251)
	{
		TunerByte5 = 0x01;
	}
	else if(dwTunerFreq < 884000)
	{
		TunerByte5 = 0x08;
	}
	else
	{
		printf("Error Input Centerfreq");
	}

	dwTunerFreq=(TunerByte4<<8) + TunerByte5;
	if (!Tnim_WriteRegisterValue(psTnim,MT352_TUNER_CONT,2,dwTunerFreq))//MT352_TUNER_CONT=0x5B
		return FALSE;

	/* calculate LO frequency*/
	dwTunerFreq=FREQUENCY(dwBWandFreqkHz);/* kHz*/
	/* IF offset*/
	if ((psTnim->psTunerInfo->Settings) & TUNER_LO_INJECTION)//TUNER_LO_INJECTION  0x02
		dwTunerFreq -= psTnim->psTunerInfo->IF1kHz;      //Setting(SEM)==0x01
	else
		dwTunerFreq += psTnim->psTunerInfo->IF1kHz;

	/* convert frequency to divider ratio*/
//	if (psTnim->psTunerTable[ucIndex-1].FcompkHzx100==0) return FALSE;//FcompKHzx100==16667
	dwTunerFreq = (dwTunerFreq * 1000) / Refer_Value;//Refer_Value = 16667
	dwTunerFreq +=5;dwTunerFreq /=10;     /*round off the result*/

	/* program the registers*/
	if (!Tnim_WriteRegisterValue(psTnim,MT352_CHAN_START,2,dwTunerFreq))
		return FALSE;
	if (!Tnim_WriteRegisterValue(psTnim,MT352_CHAN_STOP,2,dwTunerFreq))
		return FALSE;

	return TRUE;
}
#endif


#ifdef SEM_DNOS204ZH102A
bool8 Tnim_ProgramTuner(PSTNIMCTL psTnim,u32 dwBWandFreqkHz)
{
	u8 ucIndex;
	u32 dwTunerFreq;
	u16 TunerByte2,TunerByte3,TunerByte4,TunerByte5;
	u32 Refer_Value;

	Refer_Value=16667;
	/*address*/
	#if 0
	if (!RegisterWrite2wb(psTnim->DeviceID,MT352_TUNER_ADDR,//MT352_TUNER_ADDR==0x58
		&(psTnim->psTunerInfo->Address),1)) 
			return FALSE;//psTnim->psTunerInfo->Address==0xC2
	#endif

	if (!RegisterWrite2wb(psTnim->DeviceID,MT352_TUNER_ADDR,//MT352_TUNER_ADDR==0x58
		&(psTnim->psTunerInfo->Address),1)) 
			return FALSE;//psTnim->psTunerInfo->Address==0xC2

	/* Control Bytes*/
//	dwTunerFreq= (FREQUENCY(dwBWandFreqkHz))/1000; /* RF (MHz)*/
	dwTunerFreq= (FREQUENCY(dwBWandFreqkHz)); /* RF (KHz)*/
	//FREQUENCY(dwBWfreq) ((dwBWfreq) & 0x00FFFFFF)

//	TunerByte4=0x86;//DNOS204ZH101A
	TunerByte4=0x84;//DNOS204ZH102A
	/* ChargePump Setting version 1*/
	if(dwTunerFreq < 370001)
	{/*3 --> 125uA (extended)*/
		TunerByte4=TunerByte4 | 0x38;
	}
	else if(dwTunerFreq < 450001)
	{/*4 --> 250uA (extended)*/
		TunerByte4=TunerByte4 | 0x70;
	}
	else if(dwTunerFreq < 470001)
	{/*5 --> 650uA (extended)*/
		TunerByte4=TunerByte4 | 0x78;
	}
	else if(dwTunerFreq < 762000)
	{/*3 --> 125uA (extended)*/
		TunerByte4=TunerByte4 | 0x38;
	}
	else if(dwTunerFreq < 834000)
	{/*4 --> 250uA (extended)*/
		TunerByte4=TunerByte4 | 0x70;
	}
	else if(dwTunerFreq < 884001)
	{/*5 --> 650uA (extended)*/
		TunerByte4=TunerByte4 | 0x78;
	}
	else
	{
	printf("Error Input Centerfreq");
	}

	if(dwTunerFreq < 173251)
	{
		TunerByte5 = 0x01;
	}
	else if(dwTunerFreq < 470251)
	{
		TunerByte5 = 0x02;
	}
	else if(dwTunerFreq < 884000)
	{
		TunerByte5 = 0x08;
	}
	else
	{
		printf("Error Input Centerfreq");
	}

	dwTunerFreq=(TunerByte4<<8) + TunerByte5;
	if (!Tnim_WriteRegisterValue(psTnim,MT352_TUNER_CONT,2,dwTunerFreq))//MT352_TUNER_CONT=0x5B
		return FALSE;

	/* calculate LO frequency*/
	dwTunerFreq=FREQUENCY(dwBWandFreqkHz);/* kHz*/
	/* IF offset*/
	if ((psTnim->psTunerInfo->Settings) & TUNER_LO_INJECTION)//TUNER_LO_INJECTION  0x02
		dwTunerFreq -= psTnim->psTunerInfo->IF1kHz;      //Setting(SEM)==0x01
	else
		dwTunerFreq += psTnim->psTunerInfo->IF1kHz;

	/* convert frequency to divider ratio*/
//	if (psTnim->psTunerTable[ucIndex-1].FcompkHzx100==0) return FALSE;//FcompKHzx100==16667
	dwTunerFreq = (dwTunerFreq * 1000) / Refer_Value;//Refer_Value = 16667
	dwTunerFreq +=5;dwTunerFreq /=10;     /*round off the result*/

	/* program the registers*/
	if (!Tnim_WriteRegisterValue(psTnim,MT352_CHAN_START,2,dwTunerFreq))
		return FALSE;
	if (!Tnim_WriteRegisterValue(psTnim,MT352_CHAN_STOP,2,dwTunerFreq))
		return FALSE;

	return TRUE;
}
#endif

#ifdef SEM_TDTC8250
//xd_li for Jeja 8250 tuner
//7M 8M switch
bool8 TnimBandSwitching(PSTNIMCTL psTnim, u8 ucBW)
{
	u8 Band_7M=0x83, Band_8M=0x8B;

	/*Switching SAW 7/8M Band Control*/
	if(ucBW==7)
	{
		//psTnim->pfRegisterWrite(psTnim->DeviceID, MT352_GPP_CTL, &Band_7M, 1);
		RegisterWrite2wb(psTnim->DeviceID,MT352_GPP_CTL, &Band_7M,1);
	}else if(ucBW==8)
	{
		//psTnim->pfRegisterWrite(psTnim->DeviceID, MT352_GPP_CTL, &Band_8M, 1);
		RegisterWrite2wb(psTnim->DeviceID,MT352_GPP_CTL, &Band_8M,1);
	}
	/*Switching SAW 7/8M Band Control End*/
	return TRUE;
}
//xd_li for Jeja 8250 tuner
#endif

/************************Zarlink Semiconductor*********************************
*   Name:Tnim_ProgramBW()
*   Purpose:Programs the TRL register according to bandwidth
*   Remarks:Also programs NON20_8 bit as required
*	    TRL_nom_rate= 2^16 (64/7) * (ucBW/8) / Fadc(MHz)
*		        = 2^16*64*3000/7/8 * ucBW/Fadc(kHzx3)
*			=224694857.143 *ucBW/Fadc(kHzx3)
*   Inputs: Bandwidth (Mhz)
*   Outputs:FALSE if write failed
********************************************************************************/
bool8 Tnim_ProgramBW(PSTNIMCTL psTnim,u8 ucBW)
{
	u32 dwTemp;
	u8 ucBuffer;
	u16 wADCclock;


#ifdef SEM_TDTC8250
	TnimBandSwitching(psTnim, ucBW);
#endif

	wADCclock = Tnim_ADCClock_x3(psTnim);
	dwTemp = 224694857;
	dwTemp *= ucBW; /* still less than 2^32*/
	dwTemp += wADCclock/2; /* for rounding*/
	dwTemp /= wADCclock;

	if (!Tnim_WriteRegisterValue(psTnim,MT352_TRL_NOM_RATE,2,dwTemp))
		return FALSE;

	psTnim->ucBW = ucBW;
	/* NON20_8 is set if Xtal=20.48 and */
	if (!MT352_READ(MT352_CLOCK_CTL)) 
		return FALSE;

	if ((psTnim->Xtal==0) && (ucBW ==8))
		ucBuffer &=~MT352_CLKCTL_NON208;
	else
		ucBuffer |= MT352_CLKCTL_NON208;

	return MT352_WRITE(MT352_CLOCK_CTL);
}

/************************Zarlink Semiconductor*********************************
*   Name:Tnim_WriteRegisterValue()
*   Purpose:writes a value (up to 32 bits) to a number of contiguous registers
*   Remarks:Takes one or more bytes from the passed value and writes to chip
*   Inputs: reg: address of first register to write
*           cound: number of bytes to write (+ve = MSB first, -ve =LSB first)
*           value: 32 bit varibale containing data to write
*   Outputs:status
********************************************************************************/
bool8 Tnim_WriteRegisterValue(PSTNIMCTL psTnim, u8 byReg, s8 cCount,u32 dwValue)
{
	u8 Buffer[4];/* since the biggest dwValue is 4 Uint8Ts */
	s8 counter;
	
	if ((u8)ABSVAL(cCount)>sizeof(Buffer)) 
		return FALSE;
	if (cCount>0) /* MSB first */
	{
		for (counter=(s8)(cCount-1);counter>=0;counter--)
		{
			Buffer[counter]= (u8) (dwValue & 0xFF);
			dwValue>>=8; 
		}
	}
	else /* LSB first */
	{
		for (counter=0;counter<cCount;counter++)
		{
			Buffer[counter]= (u8) (dwValue & 0xFF);
			dwValue>>=8; 
		}
	}

	return RegisterWrite2wb(psTnim->DeviceID,byReg, Buffer,(u8)ABSVAL(cCount));
}

/************************Zarlink Semiconductor*********************************
*   Name:Tnim_ADCClock_x3()
*   Purpose:Determines the clock frequency from the settings
*   Remarks: 2 ADC rates are available. If tuner IF is 44.75MHz
*      and the output is at IF1, we select the lower frequency (~19.5 MHz)
*      otherwise we use the higher 20.5MHz.
*      NOTE: this means that the 19.5 Xtal option is only suitable for
*      4.57 and 44.75 MHz inputs.
*   Inputs:STnimControl Structure
*   Outputs:16bit frequency kHz x3
********************************************************************************/
u16 Tnim_ADCClock_x3(PSTNIMCTL psTnim)
{
	return g_tnim2_wADCClock_x3[psTnim->Xtal]//When psTnim->Xtal==0, Xtal=20.48
		[((psTnim->psTunerInfo->IF1kHz>40000) && ((psTnim->psTunerInfo->Settings) & TUNER_IF1_OUTPUT))?1:0]
		[psTnim->AdcPll]; //61440 wonki
}

/************************Zarlink Semiconductor*********************************
*   Name:TnimReadSNRx8()
*   Purpose:Read the signal to noise ratio
*   Remarks:returns 0 if not locked
*   Inputs:
*   Outputs: snr in dB x8
********************************************************************************/
u8 TnimReadSNRx8(PSTNIMCTL psTnim)
{
	u8 ucBuffer =0;
	TNIM_ENTRYB;

	if(Tnim_IsLocked(psTnim))
	{
		if (!MT352_READ(MT352_SNR))	 
			ucBuffer=0;//MT352_SNR=0x09
	}

	TNIM_EXIT;

	return ucBuffer;
}

/************************Zarlink Semiconductor*********************************
*   Name: Tnim_IsLocked()
*   Purpose:Reads lock status from MT352
*   Remarks:
*   Inputs:
*   Outputs:TRUE if locked
********************************************************************************/
bool8 Tnim_IsLocked(PSTNIMCTL psTnim)
{
	u8 ucBuffer;

	if (MT352_READ(MT352_CONFIG))//MT352_CONFIG=0x8A
	{
		if ((ucBuffer & MT352_CONF_ENABLE)==MT352_CONF_ENABLE)//MT352_CONF_ENABLE=0x20
		{
			if (MT352_READ(MT352_FECSTAT))//MT352_FECSTAT=0x01
			{
				return (ucBuffer & MT352_FECSTAT_LOCKED)==MT352_FECSTAT_LOCKED;//MT352_FECSTAT_LOCKED=0x06
			}
		}
	}
	return FALSE;
}

/************************Zarlink Semiconductor*********************************
*   Name:TnimReadAGC()
*   Purpose:Read the AGC values
*   Remarks:
*   Inputs:
*   Outputs:
********************************************************************************/
bool8 TnimReadAGC(PSTNIMCTL psTnim,STnimAGC * psAGC)
{
	bool8 ret;
	u32 dwAGC;
	TNIM_ENTRYB;
	ret = Tnim_ReadRegisterValue(psTnim,MT352_AGC_GAIN,4,&dwAGC);//MT352_AGC_GAIN=0x12
	if (ret)
	{
		psAGC->wTotal = (u16) (dwAGC & 0x000FFF);
		psAGC->wRFsec = (u16) ((dwAGC>>12) & 0x3FF);
		psAGC->wIFpri = (u16) ((dwAGC>>22) & 0x3FF);
	}
	TNIM_EXIT;

	return ret;
}

/************************Zarlink Semiconductor*********************************
*   Name:Tnim_ReadRegisterValue()
*   Purpose:Reads Multibyte register values;
*   Remarks: packs up to 4 bytes (msb or lsb first) into a 32 bit result
*   Inputs: reg : address of first register
*           count : number of bytes to read +ve reads MSB first, -ve reads LSB first
*   Outputs: result 32bit unsigned value
********************************************************************************/
bool8 Tnim_ReadRegisterValue(PSTNIMCTL psTnim, u8 byReg,s8 cCount,u32 * pdwValue)
{
	u8 Buffer[4]={0,0,0,0};/* only 4 Uint8Ts allowed for up to u32*/
	s16 counter;
	u32 ans = 0;
	bool8 ret;

	if ((u8) ABSVAL(cCount)>sizeof(Buffer)) 
		return FALSE;

	ans =0;
	if (RegisterRead2wb(psTnim->DeviceID,byReg, Buffer,(u8)ABSVAL(cCount)))
	{
		if (cCount>0) /* MSB first */
		{
			for (counter=0;counter<cCount;counter++)
			{
				ans <<=8;
				ans +=(Buffer[counter]);
			}
			 *pdwValue = ans;
			ret = TRUE;
		}
		else	/* LSB first*/
		{
			for (counter=(u16)(-1-cCount);counter>=0;counter--)
			{
				ans <<=8;
				ans +=(Buffer[counter]);
			}
			 *pdwValue = ans;
			ret = TRUE;
		}
	}
	else
		ret = FALSE;

	return ret;
}


/************************Zarlink Semiconductor*********************************
*   Name:Tnim_Initialise()
*   Purpose:Initialise the MT352 after power up
*   Remarks:
*   Inputs:
*   Outputs:
********************************************************************************/
bool8 Tnim_Initialise(PSTNIMCTL psTnim)
{
	u8 ucBuffer;/* one byte buffer for now */
	/*Assume we have been hardware reset */

	/* set config register*/
	ucBuffer = MT352_CONF_ENABLE |
		   MT352_CONF_TEIEN |
		   MT352_CONF_BKERRINV |
		   MT352_CONF_MDOSWAP |
		   MT352_CONF_BG12;

	if (psTnim->MpegOff) 
		ucBuffer |=MT352_CONF_MPEGDIS;
	if (psTnim->MPEGserial) 
		ucBuffer |=MT352_CONF_BSO;

	if (psTnim->NoTEI)  
		ucBuffer &=~MT352_CONF_TEIEN;
	if (psTnim->NoBKERRinvert) 
		ucBuffer &= ~MT352_CONF_BKERRINV;
	/*psTnim->NoMD0swap=1*/
	if (psTnim->NoMDOswap) 
		ucBuffer &= ~MT352_CONF_MDOSWAP;//0x02
	if (psTnim->NoMPEGgap12) 
		ucBuffer &=~MT352_CONF_BG12;
		
	//printf("config=%x\n", ucBuffer); getch();
	//ucBuffer=0x2d
	if (! MT352_WRITE(MT352_CONFIG)) 
		return FALSE;//MT352_CONFIG=0x8A

	/* set clock mode*/
	ucBuffer = (u8)(Tnim_GetClockMode(psTnim)
		+psTnim->MPEGclkinEn?MT352_CLKCTL_MCLKINEN:0
		+psTnim->NoMPEGClkInv?0:MT352_CLKCTL_MCLKINV
		+MT352_CLKCTL_ADC_ENABLE);

	//printf("config=%x\n", ucBuffer);
	//ucBuffer=0x30
	if (! MT352_WRITE(MT352_CLOCK_CTL)) 
		return FALSE;//MT352_CLOCK_CTL=0x89

	/* delay around 200礢 use dummy read*/
	if (!MT352_READ(MT352_FECSTAT)) 
		return FALSE;

	/*reset*/
	ucBuffer=MT352_RESET_ALL;//0xFF
	if (! MT352_WRITE(MT352_RESET)) 
		return FALSE;//MT352_RESET=0x50

	/* Initialise ADC (only first byte needed)*/
	ucBuffer = MT352_ADC_CTL_INIT;//0x40
	if (! MT352_WRITE(MT352_ADC_CTL)) 
		return FALSE;//MT352_ADC_CTL=0x8E

	/*tuner AGC settings (10 bytes from AGC target onwards*/
	RegisterWrite2wb(psTnim->DeviceID,MT352_AGC_TARGET,psTnim->psTunerInfo->AGC,10);
					//MT352_AGC_TARGET=0x67