mt352.c

PHILIPS1316 tuner 驱动软件用于PHILIPS TDM1316 DVB-T tuner。经过实际测试。

/**************************************************************************

        (C)Copyright Cheertek Inc. 2002-2004,
           D700, all right reserved.

        Product : STB Firmware

****************************************************************************/

#include <stdio.h>
//#include <stdlib.h>
#include <string.h>
#include "winav.h"
#include "types.h"
#include "dvb_type.h"
#include "dvb_iic.h"

#include "mt352.h"

/*macros for state machines */
/* returns TRUE if elapsed time>= x - note unsigned typecast to ensure rollover survival at 49d 17h 2m 49.295s*/
#define TNIM_TIME_ELAPSED(x) ((*(psTnim->pMilliSeconds) - psTnim->Timer)>=(x))
//#define TNIM_TIME_ELAPSED(x) (((u16) ( ((u16) *(psTnim->pMilliSeconds)) - psTnim->Timer))>=(x))

/* returns TRUE if the RS timer has expired*/
//#define TNIM_RS_TIMEOUT  (((u16) ( ((u16) *(psTnim->pMilliSeconds)) - psTnim->RStimer))>=(TNIM_RS_TIME))

/* general macros */
#define TNIM_ENTRYB	{if (!Tnim_CheckPointers(psTnim)) return FALSE;ENTER_CONTENTION_LOCK;}
#define TNIM_ENTRYV	{if (!Tnim_CheckPointers(psTnim)) return;ENTER_CONTENTION_LOCK;}
#define TNIM_COMMAND(x)	psTnim->Command = (x)
#define TNIM_EXIT	EXIT_CONTENTION_LOCK

/* text for display*/
#define TXT_OFF			"Off    "
#define TXT_STANDBY		"Standby"
#define TXT_IDLE		"Idle   "
#define TXT_BUSY		"Busy   "
#define TXT_LOCKED		"Locked "
#define TXT_SCANNING	"Scanning"
#define TXT_STOPPED     "Stopped"
#define TXT_BLANK		" ------"

/* read or wrrite one byte to/from register*/
#define MT352_WRITE(reg) RegisterWrite2wb(psTnim->DeviceID,(reg),&ucBuffer,1)
#define MT352_READ(reg)	 RegisterRead2wb(psTnim->DeviceID,(reg),&ucBuffer,1)

#define BANDWIDTH(dwBWfreq) ((u8)((dwBWfreq)>>24))
#define FREQUENCY(dwBWfreq) ((dwBWfreq) & 0x00FFFFFF)
#define MAKEBWFREQ(bwMHz,fkHz)	(( ((u32 )(bwMHz))<<24) + (fkHz) )

#define DECLARE_TNIM_TIMER static u32 dwDebugStartTime
#define RESET_TNIM_TIMER    dwDebugStartTime= *(psTnim->pMilliSeconds)
#define PRINT_TNIM_TIMER(s)    _RPT2(_CRT_WARN,"\n%s at %d ms",(s),*(psTnim->pMilliSeconds)-dwDebugStartTime)

u16 g_iDisplayMode=0;/* used to select display */

u32 g_dwClock;	/* millisecond clock*/

bool8    g_isPortOpen =FALSE;      /* Port open flag*/
bool8	g_isActive = TRUE; /* termination variable*/
bool8	g_isScanning = FALSE;
bool8    g_WantLPdata = FALSE;
u16		g_wUBC =0;
bool8	g_isPostVitUpdate = FALSE;
bool8	g_isPreVitUpdate = FALSE;
bool8	g_isRSUBCUpdate  = FALSE;

/* set up default tuner name*/
/*
char g_szTunerName[40] =
{
#if defined(ALPS_TDLB7X900)
"ALPS TDLB7X900A 4.57MHz (default)"
#elif defined (ALPS_TDLB7IF)
"ALPS TDLB7IF 36MHz (default)"
#elif defined(SEM_TECC2349PG)
"SEM TECC2349PG39L 36MHz (default)"
#elif defined(SEM_DNOS204)
"SEM DNOS204 36MHz (default)"
#else
"Unspecified default tuner"
#endif
};
*/

STnimControl g_TheTnim;     /* main structure for demodulator */

typedef struct STestScanItem
{
	STnimChannel Channel; /* required information for tuning */
	STnimAuxChannelInfo	aux; /* for interest only */
	struct STestScanItem * pNext;
}STestScanItem, *pSTestScanItem;

pSTestScanItem g_pScanListHead = NULL;    /* pointer to scan list first entry*/
pSTestScanItem g_pScanListTail = NULL;     /*pointer to scan list last entry */
int g_ChannelCount =0;


//extern unsigned long getSysTime(void); /* from zdostime.lib */

BusStatus2wb _2wb_status;
u8 PortData = 0x40;   /* global state of lpt pin*/
u8 PortControl = 0; /* global  control reg*/
u16 LPTBase = 0x378;/* define the base address*/


/*****************************GLOBAL*******************************************/
#if 1
/* default tuner tables (popluated from tuner.h) */
struct STnimTunerTable code TnimTunerTable[] = {TUNER_TABLE};
//struct STnimTunerInfo const TnimTunerInfo = {TUNER_INFO};
struct STnimTunerInfo TnimTunerInfo = {TUNER_INFO};
#endif

/*clock modes:
first index = Xtal 20.48,19.5,27,4
second index = clock mode High (~20.4MHz), Low(~19.5MHz)
third index = AdcPll from xtal(when possible),pll
*/
static u8 code g_tnim2_ucModes[4][2][2] =
{
	/*Crystal 20.48 MHz */
	MT352_CLKCTL_MODE1,	/*ADC_CLK=20.48 (xtal)*/
	MT352_CLKCTL_MODE2,	/*ADC_CLK=20.48 (pll) */
	MT352_CLKCTL_MODE5, /*ADC_CLK=19.63 (pll) */
	MT352_CLKCTL_MODE5, /*ADC_CLK=19.63 (pll) */

	/*Crystal 19.5MHz */
	MT352_CLKCTL_MODE3, /*ADC_CLK=19.5 (xtal) */
	MT352_CLKCTL_MODE4, /*ADC_CLK=19.5 (pll)  */
	MT352_CLKCTL_MODE3, /*ADC_CLK=19.5 (xtal)*/
	MT352_CLKCTL_MODE4, /*ADC_CLK=19.5 (pll)*/
	/*27*/
	MT352_CLKCTL_MODE6, /*ADC_CLK=20.25(pll) */
	MT352_CLKCTL_MODE7, /*ADC_CLK=19.29(pll) */
	MT352_CLKCTL_MODE6, /*ADC_CLK=20.25(pll) */
	MT352_CLKCTL_MODE7, /*ADC_CLK=19.29(pll) */
	/*4*/
	MT352_CLKCTL_MODE8, /*ADC_CLK=20.33(pll) */
	MT352_CLKCTL_MODE9,  /*ADC_CLK=19.67(pll) */
	MT352_CLKCTL_MODE8, /*ADC_CLK=20.33(pll) */
	MT352_CLKCTL_MODE9  /*ADC_CLK=19.67(pll) */
};
/*ADC Clock Frequencies stored x3 for accuracy
(only 19.2857 has a small error of 2ppm)
*/
static u16 code g_tnim2_wADCClock_x3[4][2][2]=
{
	/*Crystal 20.48 MHz */
	61440,		/*20.48*/
	61440,		/*20.48 */
	58880,		/*19.6266667*/
	58880,		/*19.6266667*/

	/*Crystal 19.5MHz */
	58500,		/*19.5000*/
	58500,		/*19.5000 */
	58500,		/*19.5000*/
	58500,		/*19.5000*/
	/*27*/
	60750,		/*20.250*/
	57857,		/*19.285714 */
	60750,		/*20.250*/
	57857,		/*19.285714*/
	/*4*/
	61000,		/*20.33333*/
	59000,		/*19.66667*/
	61000,		/*20.333333*/
	59000		/*19.666667*/
};

//volatile u8 PortDDR = CLOCK | DATA | EVENT; /* These pins all input, rest are output*/
//volatile u8 PortData= ENABLE; /* preset MT350 line high, rest low*/

/* defines for port access */
#define OUT_CLOCK       0x08      /* pin in control reg */
#define OUT_DATA        0x80      /* pin in data reg*/
#define OUT_ENABLE0     0x40      /* pin in data reg*/
#define OUT_ENABLE1     0x20      /* pin in data reg*/
#define OUT_ENABLE2     0x10      /* pin in data reg*/
#define OUT_ENABLE3     0x08      /* pin in data reg*/
#define OUT_ENABLE4     0x04      /* pin in data reg*/
#define OUT_ENABLE5     0x02      /* pin in data reg*/
#define OUT_ENABLE6     0x01      /* pin in data reg*/
#define IN_CLOCK        0x08      /* readback in status reg (-error)*/
#define IN_DATA         0x80      /* readback pin in status reg (busy)*/
#define IN_EVENT        0x40      /* Event input pin in status reg (-ack)*/


u32 dwFreqkHz=400000;
u8 ucBW=8;
u32 Total;


static void delay(unsigned int delay)
{
	unsigned int	i ;
	for(i=0;i<delay*250;i++) ;
}

/*Read noOfBytes into buffer from device at address deviceID, starting from Register
Message format (Zarlink Demodulator)
Start|deviceID+write|Register|start|deviceID+read|readbytes|stop.
Returns TRUE if succesful.
If FALSE, use GetError2wb() to determine cause, if required.
Operation may be protected by a mutex if provided
*/
bool8 RegisterRead2wb(u8 deviceId,u8 Register,u8 *buffer,u8 noBytesToRead)
{
	int	i ;
	u8	bReg ;

	bReg = Register ;
	for(i=0;i<noBytesToRead;i++)
	{
		if(DVB_IIC_WriteNoStop(deviceId, bReg) == FALSE)
		{
			return FALSE ; 
		}
		//if(DVB_IIC_Read_Burst(deviceId, buffer, noBytesToRead) == FALSE )
		if(DVB_IIC_Read_Burst(deviceId, &buffer[i], 1) == FALSE )
		{
			return FALSE ; 
		}
		bReg++ ;
	}		
	return (TRUE) ; 
}


/*Write noOfBytes from buffer from device at address deviceID, starting at Register.
Message format (Zarlink Demodulator)
Start|deviceID+write|Register|readbytes|stop.
Returns TRUE if succesful.
If FALSE, use GetError2wb() to determine cause, if required.
Operation may be protected by a mutex if provided
*/
bool8 RegisterWrite2wb(u8 deviceId,u8 Register, u8 *buffer,u8 noOfBytes)
{
	int i ;
	u8	bReg ;
	
	bReg = Register ;
	for(i=0;i<noOfBytes;i++)
	{
		if(DVB_IIC_Write_Burst (deviceId, bReg, &buffer[i], 1) == FALSE )
			return(FALSE) ;
		bReg ++ ;
	}		
	return (TRUE) ;
}


/* power control and intialisation*/
void TnimSetPower(PSTNIMCTL psTnim,ETnimPower ePower)
{
	TNIM_ENTRYV;
	switch (ePower)
	{
	case TNIM_OFF:TNIM_COMMAND(TNIM_COMMAND_OFF);break;//TNIM_COMMAND_OFF 1
	case TNIM_STANDBY:TNIM_COMMAND(TNIM_COMMAND_STANDBY);break;//TNIM_COMMAND_STANDBY 2
	case TNIM_RUN:TNIM_COMMAND(TNIM_COMMAND_RUN);break;//TNIM_COMMAND_RUN 3
	default:;
	}

	TNIM_EXIT;
}

/************************Zarlink Semiconductor*********************************
*   Name:Tnim_CheckPointers()
*   Purpose:checks that passed psTnim structure contains non null pointers
*   Remarks: Not much use in Windows, since uninitialised memory is 0xccc...
*   Inputs:
*   Outputs:
********************************************************************************/
bool8 Tnim_CheckPointers(PSTNIMCTL psTnim)
{
    /* check we have a Snim structure */
	if (psTnim == NULL)
	{
	return FALSE; /* basic structure missing */
	}

	/* enable is optional, so don't check it*/
	if ((RegisterRead2wb== NULL)
	|| (RegisterWrite2wb==NULL)
	|| (psTnim->pMilliSeconds==NULL)
	|| (psTnim->psTunerInfo==NULL)
	|| (psTnim->psTunerTable==NULL))
	{
		return FALSE;
	}
/*#pragma message ("MAKE SURE Tnim_CheckPointers() is up to date")*/
	return TRUE;
}


/************************Zarlink Semiconductor*********************************
*   Name: TnimAcquireFrequency()
*   Purpose:Starts Acquisition for passed frequency and bandwidth.
*   Remarks:Programs the tuner with frequency information
*           NB: if ucBW is not zero, programs the bandwidth setting
*   Inputs:
*   Outputs:
********************************************************************************/
bool8 TnimAcquireFrequency(PSTNIMCTL psTnim,u32 dwFreqkHz,u8 ucBW)
{
	bool8 ret;
	TNIM_ENTRYB;

	ret =Tnim_ProgramTuner(psTnim,MAKEBWFREQ(ucBW,dwFreqkHz));
	//MAKEBWFREQ(bwMHz,fkHz) (( ((u32 )(bwMHz))<<24) + (fkHz) )
	if (ret && ucBW) 
		ret = Tnim_ProgramBW(psTnim,ucBW);

	psTnim->Channel.Number |= 0x80; /*invalidate the channel number*/
	TNIM_COMMAND(TNIM_COMMAND_ACQUIRE);//TNIM_COMMAND_ACQUIRE 4
	TNIM_EXIT;
	return ret;
}
bool8 Tnim_AdjustOffsetkHz(PSTNIMCTL psTnim,u32 dwFreqkHz,u8 ucBW)
{
	bool8 ret;
	u8 ucBuffer;

	printf("Tnim_AdjustOffsetkHz %ld KHz, %dMHz\n", dwFreqkHz, (int)ucBW);
	ret =Tnim_ProgramTuner(psTnim,MAKEBWFREQ(ucBW,dwFreqkHz));
	//MAKEBWFREQ(bwMHz,fkHz) (( ((u32 )(bwMHz))<<24) + (fkHz) )
//	if (ret && ucBW) 
//		ret = Tnim_ProgramBW(psTnim,ucBW);

	ucBuffer=MT352_TUNER_GOAQUIRE;//MT352_TUNER_GOAQUIRE=0x01
	return MT352_WRITE(MT352_TUNER_GO);
}

/************************Zarlink Semiconductor*********************************
*   Name:Tnim_ProgramTuner()
*   Purpose:Calculates Synthesiser Frequency and programs tuner registers
*   Remarks:Programs same divider ratio into DIV_START & DIV_STOP
*			programs CNTL according to bandwidth and Frequency
*			Does not write to TUNER_GO
*   Inputs: Bandwidth (Mhz), Frequency kHz , TunerInfo and TunerTable
*   Outputs:FALSE if write failed
********************************************************************************/
#if defined(SEM_TECC2349PG)|| defined(SEM_TDTC8250)
bool8 Tnim_ProgramTuner(PSTNIMCTL psTnim,u32 dwBWandFreqkHz)
{
	u8 ucIndex;
	u32 dwTunerFreq;
	u16 TunerByte2,TunerByte3,TunerByte4,TunerByte5;
	u32 Refer_Value;
                         
	TunerByte4=0xBC;
	Refer_Value = 16667;

	/*address*/
	#if 0
	if (!RegisterWrite2wb(psTnim->DeviceID,MT352_TUNER_ADDR,//MT352_TUNER_ADDR==0x58
		&(psTnim->psTunerInfo->Address),1)) 
			return FALSE;//psTnim->psTunerInfo->Address==0xC2
	#endif

	if (!RegisterWrite2wb(psTnim->DeviceID,MT352_TUNER_ADDR,//MT352_TUNER_ADDR==0x58
		&(psTnim->psTunerInfo->Address),1)) 
			return FALSE;//psTnim->psTunerInfo->Address==0xC2

	/* Control Bytes*/
//	dwTunerFreq= (FREQUENCY(dwBWandFreqkHz))/1000; /* RF (MHz)*/
	dwTunerFreq= (FREQUENCY(dwBWandFreqkHz)); /* RF (KHz)*/
	//FREQUENCY(dwBWfreq) ((dwBWfreq) & 0x00FFFFFF)

#if 0
	for (ucIndex = psTnim->psTunerInfo->TableCount;ucIndex>1;ucIndex--)
	{
	if ((dwTunerFreq)>=psTnim->psTunerTable[ucIndex-1].FreqMHz) break;
	}

	/* Get control byte for RF frequency*/
	dwTunerFreq = psTnim->psTunerTable[ucIndex-1].Control;
	/* add in bandwidth switching */
	switch (BANDWIDTH(dwBWandFreqkHz))//BANDWIDTH(dwBWfreq) ((u8)((dwBWfreq)>>24))
	{
		case 6:dwTunerFreq |= psTnim->psTunerInfo->Control6MHz; break;
		case 7:dwTunerFreq |= psTnim->psTunerInfo->Control7MHz; break;
		case 8:dwTunerFreq |= psTnim->psTunerInfo->Control8MHz; break;
		default:;
	}
#endif

	/* ChargePump Setting version 1*/
	if(dwTunerFreq < 150001)
	{
	/*2 --> 50uA  (extended)*/
	TunerByte4=TunerByte4 & 0xB7;
	TunerByte4=TunerByte4 | 0x30;
	}
	else if(dwTunerFreq < 173001)
	{
	/*3 --> 125uA (extendeds)*/
		TunerByte4=TunerByte4 & 0xBF;
		TunerByte4=TunerByte4 | 0x38;
	}
	else if(dwTunerFreq < 250001)
	{
	/*2 --> 50uA  (extended)*/
	TunerByte4=TunerByte4 & 0xB7;
	TunerByte4=TunerByte4 | 0x30;
	}
	else if(dwTunerFreq < 400001)
	{
	/*3 --> 125uA (extended)*/
		TunerByte4=TunerByte4 & 0xBF;
		TunerByte4=TunerByte4 | 0x38;
	}
	else if(dwTunerFreq < 420001)
	{
	/*4 --> 250uA (extended)*/
		TunerByte4=TunerByte4 & 0xF7;
		TunerByte4=TunerByte4 | 0x70;
	}
	else if(dwTunerFreq < 470001)
	{
	/*5 --> 650uA (extended)*/
		TunerByte4=TunerByte4 | 0x78;
	}
	else if(dwTunerFreq < 600001)
	{
	/*3 --> 125uA (extended)*/
		TunerByte4=TunerByte4 & 0xBF;
		TunerByte4=TunerByte4 | 0x38;
	}
	else if(dwTunerFreq < 730001)
	{
	/*4 --> 250uA (extended)*/
		TunerByte4=TunerByte4 & 0xF7;
		TunerByte4=TunerByte4 | 0x70;
	}
	else if(dwTunerFreq < 864001)
	{
	/*5 --> 650uA (extended)*/
		TunerByte4=TunerByte4 | 0x78;
	}
	else
	{
	printf("Error Input Centerfreq");
	}
	/*0 --> 50uA  (normal)*/
	/*      TunerByte4=TunerByte4 & 0x8F; */
	/*1 --> 250uA (normal)*/
	/*	TunerByte4=TunerByte4 | 0x40;   */
	/*	TunerByte4=TunerByte4 & 0xCF;   */
	/*2 --> 50uA  (extended)*/
	/*	TunerByte4=TunerByte4 & 0xB7;   */
	/*	TunerByte4=TunerByte4 | 0x30;   */
	/*3 --> 125uA (extended)*/
	/*	TunerByte4=TunerByte4 & 0xBF;   */
	/*	TunerByte4=TunerByte4 | 0x38;   */
	/*4 --> 250uA (extended)*/
	/*	TunerByte4=TunerByte4 & 0xF7;   */
	/*	TunerByte4=TunerByte4 | 0x70;   */
	/*5 --> 650uA (extended)*/
	/*	TunerByte4=TunerByte4 | 0x78;   */
	/* program the control register*/

	if(dwTunerFreq < 173251)
	{
	TunerByte5 = 0x01;
	}
	else if(dwTunerFreq < 470251)
	{
	TunerByte5 = 0x02;          
	}