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📄 std_logic_1164_body.vhdl

📁 vhdl集成电路设计软件.需要用gcc-4.0.2版本编译.
💻 VHDL
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                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_StdLogicVector  ( s : std_ulogic_vector ) RETURN std_logic_vector IS        ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;        VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := sv(i);        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_StdULogicVector ( b : BIT_VECTOR        ) RETURN std_ulogic_vector IS        ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;        VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );    BEGIN        FOR i IN result'RANGE LOOP            CASE bv(i) IS                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS        ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;        VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := sv(i);        END LOOP;        RETURN result;    END;    -------------------------------------------------------------------    -- strength strippers and type convertors    -------------------------------------------------------------------    -- to_x01    -------------------------------------------------------------------    FUNCTION To_X01  ( s : std_logic_vector ) RETURN  std_logic_vector IS        ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;        VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := cvt_to_x01 (sv(i));        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01  ( s : std_ulogic_vector ) RETURN  std_ulogic_vector IS        ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;        VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := cvt_to_x01 (sv(i));        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01  ( s : std_ulogic ) RETURN  X01 IS    BEGIN        RETURN (cvt_to_x01(s));    END;    --------------------------------------------------------------------    FUNCTION To_X01  ( b : BIT_VECTOR ) RETURN  std_logic_vector IS        ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;        VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            CASE bv(i) IS                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01  ( b : BIT_VECTOR ) RETURN  std_ulogic_vector IS        ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;        VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            CASE bv(i) IS                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01  ( b : BIT ) RETURN  X01 IS    BEGIN            CASE b IS                WHEN '0' => RETURN('0');                WHEN '1' => RETURN('1');            END CASE;    END;    --------------------------------------------------------------------    -- to_x01z    -------------------------------------------------------------------    FUNCTION To_X01Z  ( s : std_logic_vector ) RETURN  std_logic_vector IS        ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;        VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := cvt_to_x01z (sv(i));        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01Z  ( s : std_ulogic_vector ) RETURN  std_ulogic_vector IS        ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;        VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := cvt_to_x01z (sv(i));        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01Z  ( s : std_ulogic ) RETURN  X01Z IS    BEGIN        RETURN (cvt_to_x01z(s));    END;    --------------------------------------------------------------------    FUNCTION To_X01Z  ( b : BIT_VECTOR ) RETURN  std_logic_vector IS        ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;        VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            CASE bv(i) IS                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01Z  ( b : BIT_VECTOR ) RETURN  std_ulogic_vector IS        ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;        VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            CASE bv(i) IS                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_X01Z  ( b : BIT ) RETURN  X01Z IS    BEGIN            CASE b IS                WHEN '0' => RETURN('0');                WHEN '1' => RETURN('1');            END CASE;    END;    --------------------------------------------------------------------    -- to_ux01    -------------------------------------------------------------------    FUNCTION To_UX01  ( s : std_logic_vector ) RETURN  std_logic_vector IS        ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;        VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := cvt_to_ux01 (sv(i));        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_UX01  ( s : std_ulogic_vector ) RETURN  std_ulogic_vector IS        ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;        VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            result(i) := cvt_to_ux01 (sv(i));        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_UX01  ( s : std_ulogic ) RETURN  UX01 IS    BEGIN        RETURN (cvt_to_ux01(s));    END;    --------------------------------------------------------------------    FUNCTION To_UX01  ( b : BIT_VECTOR ) RETURN  std_logic_vector IS        ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;        VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            CASE bv(i) IS                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_UX01  ( b : BIT_VECTOR ) RETURN  std_ulogic_vector IS        ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;        VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );    BEGIN        FOR i IN result'RANGE LOOP            CASE bv(i) IS                WHEN '0' => result(i) := '0';                WHEN '1' => result(i) := '1';            END CASE;        END LOOP;        RETURN result;    END;    --------------------------------------------------------------------    FUNCTION To_UX01  ( b : BIT ) RETURN  UX01 IS    BEGIN            CASE b IS                WHEN '0' => RETURN('0');                WHEN '1' => RETURN('1');            END CASE;    END;    -------------------------------------------------------------------    -- edge detection    -------------------------------------------------------------------    FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN BOOLEAN IS    BEGIN        RETURN (s'EVENT AND (To_X01(s) = '1') AND                            (To_X01(s'LAST_VALUE) = '0'));    END;    FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS    BEGIN        RETURN (s'EVENT AND (To_X01(s) = '0') AND                            (To_X01(s'LAST_VALUE) = '1'));    END;    -------------------------------------------------------------------    -- object contains an unknown    -------------------------------------------------------------------    FUNCTION Is_X ( s : std_ulogic_vector ) RETURN  BOOLEAN IS    BEGIN        FOR i IN s'RANGE LOOP            CASE s(i) IS                WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;                WHEN OTHERS => NULL;            END CASE;        END LOOP;        RETURN FALSE;    END;    --------------------------------------------------------------------    FUNCTION Is_X ( s : std_logic_vector  ) RETURN  BOOLEAN IS    BEGIN        FOR i IN s'RANGE LOOP            CASE s(i) IS                WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;                WHEN OTHERS => NULL;            END CASE;        END LOOP;        RETURN FALSE;    END;    --------------------------------------------------------------------    FUNCTION Is_X ( s : std_ulogic        ) RETURN  BOOLEAN IS    BEGIN        CASE s IS            WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;            WHEN OTHERS => NULL;        END CASE;        RETURN FALSE;    END;END std_logic_1164;

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