std_logic_misc-body.vhdl

vhdl集成电路设计软件.需要用gcc-4.0.2版本编译.

--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc.  All rights reserved.
-- 
-- This source file may be used and distributed without restriction 
-- provided that this copyright statement is not removed from the file 
-- and that any derivative work contains this copyright notice.
--
--	Package name: std_logic_misc
--
--	Purpose: This package defines supplemental types, subtypes, 
--		 constants, and functions for the Std_logic_1164 Package.
--
--	Author:  GWH
--
--------------------------------------------------------------------------

package body std_logic_misc is

--synopsys synthesis_off

    type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;

    --------------------------------------------------------------------
    --
    -- Truth tables for output strength --> STD_ULOGIC lookup
    --
    --------------------------------------------------------------------

    -- truth table for output strength --> STD_ULOGIC lookup
    constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE := 
    --  ------------------------------------------------------------------
    --  | X01  X0H  XL1  X0Z  XZ1  WLH  WLZ  WZH  W0H  WL1 | strn/ output|
    --  ------------------------------------------------------------------
        (('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'),  -- |   U   |
         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   X   |
         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   0   |
         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   1   |
         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   Z   |
         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   W   |
         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   L   |
         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   H   |
         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- |   -   |



    --------------------------------------------------------------------
    --
    -- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
    --
    --------------------------------------------------------------------

    -- truth table for output strength --> STD_ULOGIC lookup
    constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE := 
    --  ------------------------------------------------------------------
    --  | X01  X0H  XL1  X0Z  XZ1  WLH  WLZ  WZH  W0H  WL1 | strn/ output|
    --  ------------------------------------------------------------------
        (('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'),  -- |   U   |
         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   X   |
         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   0   |
         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   1   |
         ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'),  -- |   Z   |
         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   W   |
         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   L   |
         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   H   |
         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- |   -   |



    ---------------------------------------------------------------------
    --
    -- functions for mapping the STD_(U)LOGIC according to STRENGTH
    --
    ---------------------------------------------------------------------

    function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
	-- pragma subpgm_id 387
    begin
    	return tbl_STRN_STD_ULOGIC(input, strn);
    end strength_map;


    function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
	-- pragma subpgm_id 388
    begin
    	return tbl_STRN_STD_ULOGIC_Z(input, strn);
    end strength_map_z;


    ---------------------------------------------------------------------
    --
    -- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
    --
    ---------------------------------------------------------------------

--synopsys synthesis_on
    function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
      -- pragma built_in SYN_FEED_THRU
      -- pragma subpgm_id 389
--synopsys synthesis_off
        alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
    begin
--synopsys synthesis_off
    	return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
    end Drive;


    function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
      -- pragma built_in SYN_FEED_THRU
      -- pragma subpgm_id 390
--synopsys synthesis_off
        alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
    begin
--synopsys synthesis_off
    	return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
    end Drive;
--synopsys synthesis_off


    ---------------------------------------------------------------------
    --
    -- conversion functions for sensing various types
    --
    -- (the second argument allows the user to specify the value to
    --  be returned when the network is undriven)
    --
    ---------------------------------------------------------------------

    function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) 
    					        return STD_LOGIC is
	-- pragma subpgm_id 391
    begin
    	if V = 'Z' then
    		return vZ;
	elsif V = 'U' then
		return vU;
	elsif V = '-' then
		return vDC;
    	else
    		return V;
    	end if;
    end Sense;


    function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
    					return STD_LOGIC_VECTOR is
	-- pragma subpgm_id 392
    	alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
    	variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
    begin
    	for i in Value'range loop
    		if ( Value(i) = 'Z' ) then
    			Result(i) := vZ;
		elsif Value(i) = 'U' then
			Result(i) :=  vU;
		elsif Value(i) = '-' then
			Result(i) := vDC;
    		else
    			Result(i) := Value(i);
    		end if;
    	end loop;
    	return Result;
    end Sense;


    function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
    					return STD_ULOGIC_VECTOR is
	-- pragma subpgm_id 393
    	alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
    	variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
    begin
    	for i in Value'range loop
    		if ( Value(i) = 'Z' ) then
    			Result(i) := vZ;
		elsif Value(i) = 'U' then
			Result(i) :=  vU;
		elsif Value(i) = '-' then
			Result(i) := vDC;
    		else
    			Result(i) := Value(i);
    		end if;
    	end loop;
    	return Result;
    end Sense;


    function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
    					return STD_LOGIC_VECTOR is
	-- pragma subpgm_id 394
    	alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
    	variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
    begin
    	for i in Value'range loop
    		if ( Value(i) = 'Z' ) then
    			Result(i) := vZ;
		elsif Value(i) = 'U' then
			Result(i) :=  vU;
		elsif Value(i) = '-' then
			Result(i) := vDC;
    		else
    			Result(i) := Value(i);
    		end if;
    	end loop;
    	return Result;
    end Sense;


    function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
    					return STD_ULOGIC_VECTOR is
	-- pragma subpgm_id 395
    	alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
    	variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
    begin
    	for i in Value'range loop
    		if ( Value(i) = 'Z' ) then
    			Result(i) := vZ;
		elsif Value(i) = 'U' then
			Result(i) :=  vU;
		elsif Value(i) = '-' then
			Result(i) := vDC;
    		else
    			Result(i) := Value(i);
    		end if;
    	end loop;
    	return Result;
    end Sense;

    ---------------------------------------------------------------------
    --
    --	Function: STD_LOGIC_VECTORtoBIT_VECTOR
    --
    --	Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
    --
    --	Mapping:	0, L --> 0
    --			1, H --> 1
    --			X, W --> vX if Xflag is TRUE
    --			X, W --> 0  if Xflag is FALSE
    --			Z --> vZ if Zflag is TRUE
    --			Z --> 0  if Zflag is FALSE
    --			U --> vU if Uflag is TRUE
    --			U --> 0  if Uflag is FALSE
    --			- --> vDC if DCflag is TRUE
    --			- --> 0  if DCflag is FALSE
    --
    ---------------------------------------------------------------------

--synopsys synthesis_on
    function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
    	; vX, vZ, vU, vDC: BIT := '0'; 
    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
    		   ) return BIT_VECTOR is
      -- pragma built_in SYN_FEED_THRU
      -- pragma subpgm_id 396
--synopsys synthesis_off
    	alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
    	variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
    begin
--synopsys synthesis_off
    	for i in Value'range loop
    		case Value(i) is
    			when '0' | 'L' =>
    				Result(i) := '0';
    			when '1' | 'H' =>
    				Result(i) := '1';
	    		when 'X' =>
    				if ( Xflag ) then
    					Result(i) := vX;
    				else
    					Result(i) := '0';
	    		 		assert FALSE
    				 	    report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
    				 	    severity WARNING;
    				end if;
	    		when 'W' =>
    				if ( Xflag ) then
    					Result(i) := vX;
    				else
    					Result(i) := '0';
	    		 		assert FALSE
    				 	    report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
    				 	    severity WARNING;
    				end if;
	    		when 'Z' =>
    				if ( Zflag ) then
    					Result(i) := vZ;
	    			else
    					Result(i) := '0';
    					assert FALSE
    					    report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
    					    severity WARNING;
	    			end if;
    			when 'U' =>
    				if ( Uflag ) then
    					Result(i) := vU;
	    			else
    					Result(i) := '0';
    					assert FALSE
    					    report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
    					    severity WARNING;
				end if;
    			when '-' =>
    				if ( DCflag ) then
    					Result(i) := vDC;
	    			else
    					Result(i) := '0';
    					assert FALSE
    					    report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
    					    severity WARNING;
	    			end if;
    			end case;
	    	end loop;
    	return Result;
--synopsys synthesis_on
    end STD_LOGIC_VECTORtoBIT_VECTOR;




    ---------------------------------------------------------------------
    --
    --	Function: STD_ULOGIC_VECTORtoBIT_VECTOR
    --
    --	Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
    --
    --	Mapping:	0, L --> 0
    --			1, H --> 1
    --			X, W --> vX if Xflag is TRUE
    --			X, W --> 0  if Xflag is FALSE
    --			Z --> vZ if Zflag is TRUE
    --			Z --> 0  if Zflag is FALSE
    --			U --> vU if Uflag is TRUE
    --			U --> 0  if Uflag is FALSE
    --			- --> vDC if DCflag is TRUE
    --			- --> 0  if DCflag is FALSE
    --
    ---------------------------------------------------------------------

    function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
    	; vX, vZ, vU, vDC: BIT := '0'; 
    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
    		   ) return BIT_VECTOR is
      -- pragma built_in SYN_FEED_THRU
      -- pragma subpgm_id 397
--synopsys synthesis_off
    	alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
    	variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
    begin
--synopsys synthesis_off
    	for i in Value'range loop
    		case Value(i) is
    			when '0' | 'L' =>
    				Result(i) := '0';
    			when '1' | 'H' =>
    				Result(i) := '1';
	    		when 'X' =>
    				if ( Xflag ) then
    					Result(i) := vX;
	    			else
    					Result(i) := '0';
	    		 		assert FALSE
    				 	    report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
    				 	    severity WARNING;
	    			end if;
    			when 'W' =>
	    			if ( Xflag ) then
    					Result(i) := vX;
    				else
    					Result(i) := '0';
	    		 		assert FALSE
    				 	    report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
    				 	    severity WARNING;
	    			end if;
    			when 'Z' =>
    				if ( Zflag ) then
	    				Result(i) := vZ;
    				else
    					Result(i) := '0';
    					assert FALSE
    					    report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
	    				    severity WARNING;
    				end if;
	    		when 'U' =>
    				if ( Uflag ) then
    					Result(i) := vU;
	    			else
    					Result(i) := '0';
    					assert FALSE
    					    report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
    					    severity WARNING;
				end if;
    			when '-' =>
    				if ( DCflag ) then
    					Result(i) := vDC;
	    			else
    					Result(i) := '0';
    					assert FALSE