b3v1atemp.c

ngspice又一个电子CAD仿真软件代码.功能更全

/***********
Copyright 1990 Regents of the University of California.  All rights reserved.
Author: 1995 Min-Chie Jeng and Mansun Chan.
Modified by Paolo Nenzi 2002
File: b3v1atemp.c
**********/
/* Lmin, Lmax, Wmin, Wmax */

#include "ngspice.h"
#include "smpdefs.h"
#include "cktdefs.h"
#include "bsim3v1adef.h"
#include "const.h"
#include "sperror.h"
#include "suffix.h"

#define Kb 1.3806226e-23
#define KboQ 8.617087e-5  /* Kb / q  where q = 1.60219e-19 */
#define EPSOX 3.453133e-11
#define EPSSI 1.03594e-10
#define PI 3.141592654
#define MAX_EXP 5.834617425e14
#define MIN_EXP 1.713908431e-15
#define EXP_THRESHOLD 34.0
#define Charge_q 1.60219e-19


/* ARGSUSED */
int
BSIM3v1Atemp(GENmodel *inModel, CKTcircuit *ckt)
{ 
BSIM3v1Amodel *model = (BSIM3v1Amodel*) inModel;
BSIM3v1Ainstance *here;
struct bsim3v1aSizeDependParam *pSizeDependParamKnot, *pLastKnot, *pParam = NULL;
double tmp1, tmp2, Eg, ni, T0, T1, T2, T3, Ldrn, Wdrn;
double Temp, TRatio, Inv_L, Inv_W, Inv_LW, Vtm0, Tnom;
int Size_Not_Found;

    /*  loop through all the BSIM3v1A device models */
    for (; model != NULL; model = model->BSIM3v1AnextModel)
    {    Temp = ckt->CKTtemp;
         if (model->BSIM3v1AbulkJctPotential < 0.1)  
	     model->BSIM3v1AbulkJctPotential = 0.1;
         if (model->BSIM3v1AsidewallJctPotential < 0.1)
             model->BSIM3v1AsidewallJctPotential = 0.1;
         model->pSizeDependParamKnot = NULL;
	 pLastKnot = NULL;

	 Tnom = model->BSIM3v1Atnom;
	 TRatio = Temp / Tnom;
         
	 /* loop through all the instances of the model */
         for (here = model->BSIM3v1Ainstances; here != NULL;
              here=here->BSIM3v1AnextInstance) 
	 {    
	 
              if (here->BSIM3v1Aowner != ARCHme)
                      continue;
	      
	      pSizeDependParamKnot = model->pSizeDependParamKnot;
	      Size_Not_Found = 1;
	      while ((pSizeDependParamKnot != NULL) && Size_Not_Found)
	      {   if ((here->BSIM3v1Al == pSizeDependParamKnot->Length)
		      && (here->BSIM3v1Aw == pSizeDependParamKnot->Width))
                  {   Size_Not_Found = 0;
		      here->pParam = pSizeDependParamKnot;
		  }
		  else
		  {   pLastKnot = pSizeDependParamKnot;
		      pSizeDependParamKnot = pSizeDependParamKnot->pNext;
		  }
              }

	      if (Size_Not_Found)
	      {   pParam = (struct bsim3v1aSizeDependParam *)tmalloc(
	                    sizeof(struct bsim3v1aSizeDependParam));
                  if (pLastKnot == NULL)
		      model->pSizeDependParamKnot = pParam;
                  else
		      pLastKnot->pNext = pParam;
                  pParam->pNext = NULL;
                  here->pParam = pParam;

		     Ldrn = here->BSIM3v1Al;
		     Wdrn = here->BSIM3v1Aw;
		  
                  T0 = pow(Ldrn, model->BSIM3v1ALln);
                  T1 = pow(Wdrn, model->BSIM3v1ALwn);
                  tmp1 = model->BSIM3v1ALl / T0 + model->BSIM3v1ALw / T1
                       + model->BSIM3v1ALwl / (T0 * T1);
                  pParam->BSIM3v1Adl = model->BSIM3v1ALint + tmp1;
                  pParam->BSIM3v1Adlc = model->BSIM3v1Adlc + tmp1;

                  T2 = pow(Ldrn, model->BSIM3v1AWln);
                  T3 = pow(Wdrn, model->BSIM3v1AWwn);
                  tmp2 = model->BSIM3v1AWl / T2 + model->BSIM3v1AWw / T3
                       + model->BSIM3v1AWwl / (T2 * T3);
                  pParam->BSIM3v1Adw = model->BSIM3v1AWint + tmp2;
                  pParam->BSIM3v1Adwc = model->BSIM3v1Adwc + tmp2;

                  pParam->BSIM3v1Aleff = here->BSIM3v1Al - 2.0 * pParam->BSIM3v1Adl;
                  if (pParam->BSIM3v1Aleff <= 0.0)
	          {   IFuid namarray[2];
                      namarray[0] = model->BSIM3v1AmodName;
                      namarray[1] = here->BSIM3v1Aname;
                      (*(SPfrontEnd->IFerror))(ERR_FATAL,
                      "BSIM3v1A: mosfet %s, model %s: Effective channel length <= 0",
                       namarray);
                      return(E_BADPARM);
                  }

                  pParam->BSIM3v1Aweff = here->BSIM3v1Aw - 2.0 * pParam->BSIM3v1Adw;
                  if (pParam->BSIM3v1Aweff <= 0.0)
	          {   IFuid namarray[2];
                      namarray[0] = model->BSIM3v1AmodName;
                      namarray[1] = here->BSIM3v1Aname;
                      (*(SPfrontEnd->IFerror))(ERR_FATAL,
                      "BSIM3v1A: mosfet %s, model %s: Effective channel width <= 0",
                       namarray);
                      return(E_BADPARM);
                  }

                  pParam->BSIM3v1AleffCV = here->BSIM3v1Al - 2.0 * pParam->BSIM3v1Adlc;
                  if (pParam->BSIM3v1AleffCV <= 0.0)
	          {   IFuid namarray[2];
                      namarray[0] = model->BSIM3v1AmodName;
                      namarray[1] = here->BSIM3v1Aname;
                      (*(SPfrontEnd->IFerror))(ERR_FATAL,
                      "BSIM3v1A: mosfet %s, model %s: Effective channel length for C-V <= 0",
                       namarray);
                      return(E_BADPARM);
                  }

                  pParam->BSIM3v1AweffCV = here->BSIM3v1Aw - 2.0 * pParam->BSIM3v1Adwc;
                  if (pParam->BSIM3v1AweffCV <= 0.0)
	          {   IFuid namarray[2];
                      namarray[0] = model->BSIM3v1AmodName;
                      namarray[1] = here->BSIM3v1Aname;
                      (*(SPfrontEnd->IFerror))(ERR_FATAL,
                      "BSIM3v1A: mosfet %s, model %s: Effective channel width for C-V <= 0",
                       namarray);
                      return(E_BADPARM);
                  }

	          model->BSIM3v1Avcrit = CONSTvt0 * log(CONSTvt0
				    / (CONSTroot2 * 1.0e-14));
                  model->BSIM3v1Afactor1 = sqrt(EPSSI / EPSOX * model->BSIM3v1Atox);


		  if (model->BSIM3v1AbinUnit == 1)
		  {   Inv_L = 1.0e-6 / pParam->BSIM3v1Aleff;
		      Inv_W = 1.0e-6 / pParam->BSIM3v1Aweff;
		      Inv_LW = 1.0e-12 / (pParam->BSIM3v1Aleff
			     * pParam->BSIM3v1Aweff);
		  }
		  else
		  {   Inv_L = 1.0 / pParam->BSIM3v1Aleff;
		      Inv_W = 1.0 / pParam->BSIM3v1Aweff;
		      Inv_LW = 1.0 / (pParam->BSIM3v1Aleff
			     * pParam->BSIM3v1Aweff);
		  }
		  pParam->BSIM3v1Acdsc = model->BSIM3v1Acdsc
				    + model->BSIM3v1Alcdsc * Inv_L
				    + model->BSIM3v1Awcdsc * Inv_W
				    + model->BSIM3v1Apcdsc * Inv_LW;
		  pParam->BSIM3v1Acdscb = model->BSIM3v1Acdscb
				     + model->BSIM3v1Alcdscb * Inv_L
				     + model->BSIM3v1Awcdscb * Inv_W
				     + model->BSIM3v1Apcdscb * Inv_LW; 
				     
    		  pParam->BSIM3v1Acdscd = model->BSIM3v1Acdscd
				     + model->BSIM3v1Alcdscd * Inv_L
				     + model->BSIM3v1Awcdscd * Inv_W
				     + model->BSIM3v1Apcdscd * Inv_LW; 
				     
		  pParam->BSIM3v1Acit = model->BSIM3v1Acit
				   + model->BSIM3v1Alcit * Inv_L
				   + model->BSIM3v1Awcit * Inv_W
				   + model->BSIM3v1Apcit * Inv_LW;
		  pParam->BSIM3v1Anfactor = model->BSIM3v1Anfactor
				       + model->BSIM3v1Alnfactor * Inv_L
				       + model->BSIM3v1Awnfactor * Inv_W
				       + model->BSIM3v1Apnfactor * Inv_LW;
		  pParam->BSIM3v1Axj = model->BSIM3v1Axj
				  + model->BSIM3v1Alxj * Inv_L
				  + model->BSIM3v1Awxj * Inv_W
				  + model->BSIM3v1Apxj * Inv_LW;
		  pParam->BSIM3v1Avsat = model->BSIM3v1Avsat
				    + model->BSIM3v1Alvsat * Inv_L
				    + model->BSIM3v1Awvsat * Inv_W
				    + model->BSIM3v1Apvsat * Inv_LW;
		  pParam->BSIM3v1Aat = model->BSIM3v1Aat
				  + model->BSIM3v1Alat * Inv_L
				  + model->BSIM3v1Awat * Inv_W
				  + model->BSIM3v1Apat * Inv_LW;
		  pParam->BSIM3v1Aa0 = model->BSIM3v1Aa0
				  + model->BSIM3v1Ala0 * Inv_L
				  + model->BSIM3v1Awa0 * Inv_W
				  + model->BSIM3v1Apa0 * Inv_LW; 
				  
		  pParam->BSIM3v1Aags = model->BSIM3v1Aags
				  + model->BSIM3v1Alags * Inv_L
				  + model->BSIM3v1Awags * Inv_W
				  + model->BSIM3v1Apags * Inv_LW;
				  
		  pParam->BSIM3v1Aa1 = model->BSIM3v1Aa1
				  + model->BSIM3v1Ala1 * Inv_L
				  + model->BSIM3v1Awa1 * Inv_W
				  + model->BSIM3v1Apa1 * Inv_LW;
		  pParam->BSIM3v1Aa2 = model->BSIM3v1Aa2
				  + model->BSIM3v1Ala2 * Inv_L
				  + model->BSIM3v1Awa2 * Inv_W
				  + model->BSIM3v1Apa2 * Inv_LW;
		  pParam->BSIM3v1Aketa = model->BSIM3v1Aketa
				    + model->BSIM3v1Alketa * Inv_L
				    + model->BSIM3v1Awketa * Inv_W
				    + model->BSIM3v1Apketa * Inv_LW;
		  pParam->BSIM3v1Ansub = model->BSIM3v1Ansub
				    + model->BSIM3v1Alnsub * Inv_L
				    + model->BSIM3v1Awnsub * Inv_W
				    + model->BSIM3v1Apnsub * Inv_LW;
		  pParam->BSIM3v1Anpeak = model->BSIM3v1Anpeak
				     + model->BSIM3v1Alnpeak * Inv_L
				     + model->BSIM3v1Awnpeak * Inv_W
				     + model->BSIM3v1Apnpeak * Inv_LW;
		  pParam->BSIM3v1Angate = model->BSIM3v1Angate
				     + model->BSIM3v1Alngate * Inv_L
				     + model->BSIM3v1Awngate * Inv_W
				     + model->BSIM3v1Apngate * Inv_LW;
		  pParam->BSIM3v1Agamma1 = model->BSIM3v1Agamma1
				      + model->BSIM3v1Algamma1 * Inv_L
				      + model->BSIM3v1Awgamma1 * Inv_W
				      + model->BSIM3v1Apgamma1 * Inv_LW;
		  pParam->BSIM3v1Agamma2 = model->BSIM3v1Agamma2
				      + model->BSIM3v1Algamma2 * Inv_L
				      + model->BSIM3v1Awgamma2 * Inv_W
				      + model->BSIM3v1Apgamma2 * Inv_LW;
		  pParam->BSIM3v1Avbx = model->BSIM3v1Avbx
				   + model->BSIM3v1Alvbx * Inv_L
				   + model->BSIM3v1Awvbx * Inv_W
				   + model->BSIM3v1Apvbx * Inv_LW;
		  pParam->BSIM3v1Avbm = model->BSIM3v1Avbm
				   + model->BSIM3v1Alvbm * Inv_L
				   + model->BSIM3v1Awvbm * Inv_W
				   + model->BSIM3v1Apvbm * Inv_LW;
		  pParam->BSIM3v1Axt = model->BSIM3v1Axt
				   + model->BSIM3v1Alxt * Inv_L
				   + model->BSIM3v1Awxt * Inv_W
				   + model->BSIM3v1Apxt * Inv_LW;
		  pParam->BSIM3v1Ak1 = model->BSIM3v1Ak1
				  + model->BSIM3v1Alk1 * Inv_L
				  + model->BSIM3v1Awk1 * Inv_W
				  + model->BSIM3v1Apk1 * Inv_LW;
		  pParam->BSIM3v1Akt1 = model->BSIM3v1Akt1
				   + model->BSIM3v1Alkt1 * Inv_L
				   + model->BSIM3v1Awkt1 * Inv_W
				   + model->BSIM3v1Apkt1 * Inv_LW;
		  pParam->BSIM3v1Akt1l = model->BSIM3v1Akt1l
				    + model->BSIM3v1Alkt1l * Inv_L
				    + model->BSIM3v1Awkt1l * Inv_W
				    + model->BSIM3v1Apkt1l * Inv_LW;
		  pParam->BSIM3v1Ak2 = model->BSIM3v1Ak2
				  + model->BSIM3v1Alk2 * Inv_L
				  + model->BSIM3v1Awk2 * Inv_W
				  + model->BSIM3v1Apk2 * Inv_LW;
		  pParam->BSIM3v1Akt2 = model->BSIM3v1Akt2
				   + model->BSIM3v1Alkt2 * Inv_L
				   + model->BSIM3v1Awkt2 * Inv_W
				   + model->BSIM3v1Apkt2 * Inv_LW;
		  pParam->BSIM3v1Ak3 = model->BSIM3v1Ak3
				  + model->BSIM3v1Alk3 * Inv_L
				  + model->BSIM3v1Awk3 * Inv_W
				  + model->BSIM3v1Apk3 * Inv_LW;
		  pParam->BSIM3v1Ak3b = model->BSIM3v1Ak3b
				   + model->BSIM3v1Alk3b * Inv_L
				   + model->BSIM3v1Awk3b * Inv_W
				   + model->BSIM3v1Apk3b * Inv_LW;
		  pParam->BSIM3v1Aw0 = model->BSIM3v1Aw0
				  + model->BSIM3v1Alw0 * Inv_L
				  + model->BSIM3v1Aww0 * Inv_W
				  + model->BSIM3v1Apw0 * Inv_LW;
		  pParam->BSIM3v1Anlx = model->BSIM3v1Anlx
				   + model->BSIM3v1Alnlx * Inv_L
				   + model->BSIM3v1Awnlx * Inv_W
				   + model->BSIM3v1Apnlx * Inv_LW;
		  pParam->BSIM3v1Advt0 = model->BSIM3v1Advt0
				    + model->BSIM3v1Aldvt0 * Inv_L
				    + model->BSIM3v1Awdvt0 * Inv_W
				    + model->BSIM3v1Apdvt0 * Inv_LW;
		  pParam->BSIM3v1Advt1 = model->BSIM3v1Advt1
				    + model->BSIM3v1Aldvt1 * Inv_L
				    + model->BSIM3v1Awdvt1 * Inv_W
				    + model->BSIM3v1Apdvt1 * Inv_LW;
		  pParam->BSIM3v1Advt2 = model->BSIM3v1Advt2
				    + model->BSIM3v1Aldvt2 * Inv_L
				    + model->BSIM3v1Awdvt2 * Inv_W
				    + model->BSIM3v1Apdvt2 * Inv_LW;
		  pParam->BSIM3v1Advt0w = model->BSIM3v1Advt0w
				    + model->BSIM3v1Aldvt0w * Inv_L
				    + model->BSIM3v1Awdvt0w * Inv_W
				    + model->BSIM3v1Apdvt0w * Inv_LW;
		  pParam->BSIM3v1Advt1w = model->BSIM3v1Advt1w
				    + model->BSIM3v1Aldvt1w * Inv_L
				    + model->BSIM3v1Awdvt1w * Inv_W
				    + model->BSIM3v1Apdvt1w * Inv_LW;
		  pParam->BSIM3v1Advt2w = model->BSIM3v1Advt2w
				    + model->BSIM3v1Aldvt2w * Inv_L
				    + model->BSIM3v1Awdvt2w * Inv_W
				    + model->BSIM3v1Apdvt2w * Inv_LW;
		  pParam->BSIM3v1Adrout = model->BSIM3v1Adrout
				     + model->BSIM3v1Aldrout * Inv_L
				     + model->BSIM3v1Awdrout * Inv_W
				     + model->BSIM3v1Apdrout * Inv_LW;
		  pParam->BSIM3v1Adsub = model->BSIM3v1Adsub
				    + model->BSIM3v1Aldsub * Inv_L
				    + model->BSIM3v1Awdsub * Inv_W
				    + model->BSIM3v1Apdsub * Inv_LW;