ffuart.cpp

浙江大学的悟空嵌入式系统模拟器

/*
*  Copyright (c) 2005 Zhejiang University, P.R.China
*
*  This program is free software; you can redistribute it and/or modify
*  it under the terms of the GNU General Public License as published by
*  the Free Software Foundation; either version 2 of the License, or
*  (at your option) any later version.
*
*  This program is distributed in the hope that it will be useful,
*  but WITHOUT ANY WARRANTY; without even the implied warranty of
*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*  GNU General Public License for more details.
*
*  You should have received a copy of the GNU General Public License
*  along with this program; if not, write to the Free Software
*  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ 

//=============================================================================
/**
*  \file   FFUART.cpp
*
*  $Id: FFUART.cpp,v 1.2 2005/06/21 02:57:49 qilj Exp $
*
*  \author  Lingjie Qi <[e-mail]> 
*/
//=============================================================================

#include "./FFUART.h"
#include "Core/System.h"
#include "Core/Memory.h"
#include "Core/Processor.h"
#include "Core/Board.h"
#include "Core/Log.h"
#include"Arch/ARM/Board_PXA_Lubbock.h"

#include<io.h>

namespace DEVICE {

	void FFUART::on_reset()
	{
		for(int i=0; i<FFUART::FFUART_REG_END; ++i)
		{
			ffuart_reg_[i] = 0;
		}
	}


	void FFUART::on_mapped_memory_read(Core::u32 start, size_t size,        \
		Core::Bytecode_Type & buffer)
	{
		Core::u32 target = 0;
		Core::u32 FFUART_IRQ = (1 << 22);
		ARM::Board_PXA_Lubbock * board = (ARM::Board_PXA_Lubbock * ) Core::Wukong_Get_System().get_board();
		Core::u32 & ICPR = board->get_ICPR();
		Core::u32 & ICIP = board->get_ICIP();
		switch ( start ) 
		{
			case 0x40100000:     //FFRBR   
				target =ffuart_reg_[FFRBR] & 0xff;
				ICPR &= ~FFUART_IRQ;
				ICIP &= ~FFUART_IRQ;
				ffuart_reg_[FFIIR] &= ~0x4;
				ffuart_reg_[FFIIR] |= 0x1;
				ffuart_reg_[FFLSR]  &= ~0x1;
				Core::Wukong_Get_System().convert_to_bytecode(target, buffer);
				break;
			case 0x40100004:       //FFIER
				Core::Wukong_Get_System().convert_to_bytecode(ffuart_reg_[FFIER], buffer);
				break;
			case 0x40100008:        //FFIIR  //read only
				target= ffuart_reg_[FFIIR]  & 0xcf ;
				ICPR &= ~FFUART_IRQ;
				ICIP &= ~FFUART_IRQ;
				Core::Wukong_Get_System().convert_to_bytecode(target, buffer);
				break;
			case 0x4010000C:   //FFLCR
				Core::Wukong_Get_System().convert_to_bytecode(ffuart_reg_[FFLCR], buffer);
				break;
			case 0x40100014:   //FFLSR  //read only 
				ffuart_reg_[FFLSR] |=0x60; 
				target=ffuart_reg_[FFLSR] & 0xff ;		
				Core::Wukong_Get_System().convert_to_bytecode(target, buffer);
				break;
			//default:
				//return Core::Dummy_MMU<Core::u32>::MEMORY_IO_RW;
				//Core::Wukong_Get_System().convert_to_bytecode(target, buffer);
		}
	}

	void FFUART::on_mapped_memory_write(Core::u32 start, size_t  size, Core::Bytecode_Type & buffer)
	{
		Core::u32 target = 0;
		Core::Wukong_Get_System().convert_from_bytecode(buffer, target);
		switch ( start ) 
		{
		case 0x40100000:     //FFTHR    
			{     
				char c = target;
	
				WUKONG_STDOUT<<c;
				WUKONG_STDOUT.flush();

				ffuart_reg_[FFIIR] &=~0x2;
				ffuart_reg_[FFIIR] |=0x1;
				ffuart_reg_[FFLSR] &=~0x60;
			}
			break;
		case 0x40100004:      //FFIER
			ffuart_reg_[FFIER] = target & 0xff; 
			break;
		case 0x40100008:        //FFFCR  //write only
			ffuart_reg_[FFFCR] = target & 0xc7 ;
			break;
		case 0x4010000C:        //FFLCR
			ffuart_reg_[FFLCR] = target & 0xff;
			break;
		//default:	
			//return Core::Dummy_MMU<Core::u32>::MEMORY_IO_RW;
		}
	}

} //namespace