memory_instruction.cpp

浙江大学的悟空嵌入式系统模拟器

/* -*- C++ -*- */

/**
*  Copyright (c) 2005 Zhejiang University, P.R.China
*
*  This program is free software; you can redistribute it and/or modify
*  it under the terms of the GNU General Public License as published by
*  the Free Software Foundation; either version 2 of the License, or
*  (at your option) any later version.
*
*  This program is distributed in the hope that it will be useful,
*  but WITHOUT ANY WARRANTY; without even the implied warranty of
*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*  GNU General Public License for more details.
*
*  You should have received a copy of the GNU General Public License
*  along with this program; if not, write to the Free Software
*  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

///==================================================
/**
* @file        Memory_Instruction.cpp
* @brief      
* @author      Chenfeng Zhou <[e-mail]> 
*
* Created    : <2005-02-12 11:09:48 by Cheney Chow>
* Last update: <2005-02-12 11:39:32 by Cheney Chow>
*
* $Id: Memory_Instruction.cpp,v 1.1 2005/06/16 06:01:47 qilj Exp $
*/
///==================================================

#include "Instruction.h"
#include "Instr_Declare.h"
#include "Parser.h"
#include "Types.h"
#include "Reg_Utils.h"
#include "Utils/Debug.h"
#include "MMU.h"

namespace PPC {

	PPC_INSTRUCTION_IMPL(op_eieio)
	{
		PPC_TRACE("eieio\n");
	}

	PPC_INSTRUCTION_IMPL(op_isync)
	{
		PPC_TRACE("isync\n");
	}

	PPC_INSTRUCTION_IMPL(op_sync)
	{
		PPC_TRACE("sync\n");
	}

	PPC_INSTRUCTION_IMPL(op_lwarx)
	{
		PPC_TRACE("lwarx\n");

		PPC_s32 D, A, B;
		X_Form_Parser::parse_x(instr, D, A, B);

		PPC_Address_T start = (A? REG_TO_INT(REG(A)) : 0) + REG_TO_INT(REG(B));
		Core::Bytecode_Type buffer;
		Core::u32 val;

		if (GET_MMU().access(Core::Memory_32Bit::MEMORY_READ, start, 4, buffer) == MMU::ACCESS_FAULT)
			PPC_TRACE_RETURN("mmu read error!\n");

		Core::Wukong_Get_System().convert_from_bytecode(buffer, val);

		REG(D).convert_from_int(val);

		GET_CPU().get_cpu_state().have_reservation = true;
		GET_CPU().get_cpu_state().reservation = val;
	}

	PPC_INSTRUCTION_IMPL(op_stwcx_)
	{
		PPC_TRACE("stwcx.\n");

		PPC_s32 S, A, B;
		X_Form_Parser::parse_x(instr, S, A, B);

		PPC_Address_T start = (A? REG_TO_INT(REG(A)) : 0) + REG_TO_INT(REG(B));
		Core::Bytecode_Type buffer;
		Core::u32 val;

		REG_CLEAR_CR0();

		if (GET_CPU().get_cpu_state().have_reservation) {
			GET_CPU().get_cpu_state().have_reservation = false;

			if (GET_MMU().access(Core::Memory_32Bit::MEMORY_READ, start, 4, buffer) == MMU::ACCESS_FAULT)
				PPC_TRACE_RETURN("Mem read error!\n");

			Core::Wukong_Get_System().convert_from_bytecode(buffer, val);

			//! We make sure that the memory cell `lwarx' has accessed 
			//! is intact from other cpus, if any;

			//! From kernel's perspective,
			//! I think the atomic operation is not gurateed even by hardware;
			//! But the user may chek CR0[EQ] to confirm whether the operation
			//! is successful.
			//!												--- zcf

			if (val == GET_CPU().get_cpu_state().reservation) {
				Core::Wukong_Get_System().convert_to_bytecode((Core::u32)REG_TO_INT(REG(S)), buffer);

				if (GET_MMU().access(Core::Memory_32Bit::MEMORY_WRITE, start, 4, buffer) == MMU::ACCESS_FAULT)
					PPC_TRACE_RETURN("mmu write error!\n");

				REG_SET_BIT(CR, Reg_Flag::CR0_EQ);
			}

			if (REG_BIT_IS_SET(XER, Reg_Flag::XER_SO))
				REG_SET_BIT(CR, Reg_Flag::CR0_SO);
		}
	}

} //namespace PPC