exception_handler.cpp

浙江大学的悟空嵌入式系统模拟器

/**
*  Copyright (c) 2005 Zhejiang University, P.R.China
*
*  This program is free software; you can redistribute it and/or modify
*  it under the terms of the GNU General Public License as published by
*  the Free Software Foundation; either version 2 of the License, or
*  (at your option) any later version.
*
*  This program is distributed in the hope that it will be useful,
*  but WITHOUT ANY WARRANTY; without even the implied warranty of
*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*  GNU General Public License for more details.
*
*  You should have received a copy of the GNU General Public License
*  along with this program; if not, write to the Free Software
*  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

///==================================================
/**
* @file        Exception_Handler.cpp
* @brief      
* @author      Chenfeng Zhou <[e-mail]> 
*
* Created    : <2005-03-07 19:50:41 by Cheney Chow>
* Last update: <2005-03-07 19:58:23 by Cheney Chow>
*
* $Id: Exception_Handler.cpp,v 1.1 2005/06/16 06:01:45 qilj Exp $
*/
///==================================================

#include "Reg_Utils.h"
#include "Exception.h"
#include "Utils/Logger.h"

namespace PPC 
{
	void DSI_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		PPC_TRACE("DSI exception\n");

		REG(SRR0).convert_from_int(GET_CPU().get_pc());
#ifdef PPC7XX
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)) & 0x87c0ffff);
		REG(DAR).convert_from_int(a);
		REG(DSISR).convert_from_int(flag);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif
		// TODO: do sth with DEAR, ESR?
		REG(MSR).convert_from_int(0);

#ifdef PPC7XX
		GET_CPU().set_npc(Exception::VEC_DSI);
#else
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR2))));
#endif
	}

	void ISI_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		PPC_TRACE("ISI exception\n");

		REG(SRR0).convert_from_int(GET_CPU().get_pc());
#ifdef PPC7XX
		REG(SRR1).convert_from_int((REG_TO_INT(REG(MSR)) & 0x87c0ffff) | flag);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif
		REG(MSR).convert_from_int(0);

#ifdef PPC7XX
		GET_CPU().set_npc(Exception::VEC_ISI);
#else
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR3))));
#endif
	}

	void DEC_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		REG(SRR0).convert_from_int(GET_CPU().get_pc());
#ifdef PPC7XX
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)) & 0x87c0ffff);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif

		REG(MSR).convert_from_int(0);

#ifdef PPC7XX
			GET_CPU().set_npc(Exception::VEC_DEC);
#else
			GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR10))));
#endif
	}

	void EXT_INT_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		REG(SRR0).convert_from_int(GET_CPU().get_pc());
#ifdef PPC7XX
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)) & 0x87c0ffff);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif
		REG(MSR).convert_from_int(0);

#ifdef PPC7XX
		GET_CPU().set_npc(Exception::VEC_EXT_INT);
#else
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR4))));
#endif

	}

	void SC_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		// Store npc here!
		REG(SRR0).convert_from_int(GET_CPU().get_npc());
#ifdef PPC7XX
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)) & 0x87c0ffff);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif

		REG(MSR).convert_from_int(0);

#ifdef PPC7XX
			GET_CPU().set_npc(Exception::VEC_SC);
#else
			GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR8))));
#endif
	}

	void NO_FPU_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		REG(SRR0).convert_from_int(GET_CPU().get_pc());
#ifdef PPC7XX
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)) & 0x87c0ffff);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif

		REG(MSR).convert_from_int(0);
#ifdef PPC7XX
		GET_CPU().set_npc(Exception::VEC_NO_FPU);
#else
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR7))));
#endif
	}

	void PROGRAM_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		if (flag & Exception::EXC_PROGRAM_NEXT)
			REG(SRR0).convert_from_int(GET_CPU().get_npc());
		else
			REG(SRR0).convert_from_int(GET_CPU().get_pc());

#ifdef PPC7XX
		REG(SRR1).convert_from_int((REG_TO_INT(REG(MSR)) & 0x87c0ffff) | flag);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif

		REG(MSR).convert_from_int(0);
#ifdef PPC7XX
		GET_CPU().set_npc(Exception::VEC_PROGRAM);
#else
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR6))));
#endif
	}

	void FLOAT_ASSIT_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		REG(SRR0).convert_from_int(GET_CPU().get_pc());
#ifdef PPC7XX
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)) & 0x87c0ffff);
#else
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
#endif

		REG(MSR).convert_from_int(0);
		GET_CPU().set_npc(Exception::VEC_FLOAT_ASSIST);
	}

	void MACHINE_CHECK_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		if (!REG_BIT_IS_SET(MSR, Reg_Flag::MSR_ME)) {
			PPC_ERROR(("machine check exception: MSR[ME]=0!\n"));
			PPC_ASSERT(0);
		}

		REG(SRR0).convert_from_int(GET_CPU().get_pc());
		REG(SRR1).convert_from_int((REG_TO_INT(REG(MSR)) & 0x87c0ffff) | (1 << Reg_Flag::MSR_RI));

		REG(MSR).convert_from_int(0);
#ifdef PPC7XX
		GET_CPU().set_npc(Exception::VEC_MACHINE_CHECK);
#else
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR1))));
#endif
	}

	void TRACE_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		REG(SRR0).convert_from_int(GET_CPU().get_pc());
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)) & 0x87c0ffff);

		REG(MSR).convert_from_int(0);
		GET_CPU().set_npc(Exception::VEC_TRACE);
	}

	void INSTR_TLB_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		PPC_TRACE("INSTR_TLB exception\n");
		PPC_SHOW("INSTR_TLB exception\n");

		REG(SRR0).convert_from_int(GET_CPU().get_pc());
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));
		REG(MSR).convert_from_int(0);
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR14))));
	}

	void DATA_TLB_Handler::handle(Core::u32 flag, Core::u32 a)
	{
		PPC_SHOW("DATA_TLB exception\n");
		PPC_TRACE("DATA_TLB exception\n");

		REG(SRR0).convert_from_int(GET_CPU().get_pc());
		REG(SRR1).convert_from_int(REG_TO_INT(REG(MSR)));

		//Todo: do sth with DEAR, ESR
		REG(MSR).convert_from_int(0);
		GET_CPU().set_npc(gen_interupt_vec(REG_TO_INT(REG(IVOR13))));
	}
} //namespace PPC