register.h

浙江大学的悟空嵌入式系统模拟器

/**
 *  Copyright (c) 2005 Zhejiang University, P.R.China
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */ 

//=============================================================================
/**
 *  \file    Processor/CPU/PPC/Register.h
 *
 *  \brief   The index of each ppc register in register file
 *
 *  \author  Chenfeng Zhou <[e-mail]>
 *
 *  Created    : <2005-02-05 14:33:32 by Cheney Chow>
 *  Last update: <2005-02-12 11:59:13 by Cheney Chow>
 *
 *  $Id: Register.h,v 1.1 2005/06/16 06:01:51 qilj Exp $
 */
//=============================================================================

#ifndef _PPC_REGISTER_H_
#define _PPC_REGISTER_H_


namespace PPC {
    
    typedef enum {
        //! Generated mainly by Python;

        //! UISA register set;
        //! GPRs
        GPR0 = 0,
        GPR1,
        GPR2,
        GPR3,
        GPR4,
        GPR5,
        GPR6,
        GPR7,
        GPR8,
        GPR9,
        GPR10,
        GPR11,
        GPR12,
        GPR13,
        GPR14,
        GPR15,
        GPR16,
        GPR17,
        GPR18,
        GPR19,
        GPR20,
        GPR21,
        GPR22,
        GPR23,
        GPR24,
        GPR25,
        GPR26,
        GPR27,
        GPR28,
        GPR29,
        GPR30,
        GPR31,

        //! FPRs
		//! Actually, PPC440 doesn't have FPU in core; Need by PPC7xx...
        FPR0,
        FPR1,
        FPR2,
        FPR3,
        FPR4,
        FPR5,
        FPR6,
        FPR7,
        FPR8,
        FPR9,
        FPR10,
        FPR11,
        FPR12,
        FPR13,
        FPR14,
        FPR15,
        FPR16,
        FPR17,
        FPR18,
        FPR19,
        FPR20,
        FPR21,
        FPR22,
        FPR23,
        FPR24,
        FPR25,
        FPR26,
        FPR27,
        FPR28,
        FPR29,
        FPR30,
        FPR31,

        //! Condition Register
        CR,

        //! Floating-Point status and control register
        FPSCR,

        //! XER
        XER,

        //! Link Register
        LR,

        //! Count Register
        CTR,

        //! VEA register set
        //! Time base

        //! OEA register set
        //! Machine State Register
        MSR,

        //! Processor Version Register
        PVR,

        //! Memory Management
        //! Instruction Bat (upper and lower)
        IBATU0,  //spr528
        IBATU1,  //spr530
        IBATU2,  //spr532
        IBATU3,  //spr534

        IBATL0,  //spr529
        IBATL1,  //spr531
        IBATL2,  //spr533
        IBATL3,  //spr535

        //! Data Bat (upper and lower)
        DBATU0,  //spr536
        DBATU1,  //spr538
        DBATU2,  //spr540
        DBATU3,  //spr542

        DBATL0,  //spr537
        DBATL1,  //spr539
        DBATL2,  //spr541
        DBATL3,  //spr543

        //! SDR1 page table base address
        SDR1,

        //! SR Segment Register
        //? maybe has 16 SRs?
        SR,

        //! Exception Related
        //! Data Address Register
        DAR,

        //! Identifies the cause of DSI and alignment exceptions
        DSISR,

        //! performing a fast state save or
        //! for supporting multiprocessor implementations
        SPRG0,
        SPRG1,
        SPRG2,
        SPRG3,
		//! PPC44x specific
		SPRG4,
		SPRG5,
		SPRG6,
		SPRG7,

        //! Machine Status Save/Restore Register
    
        //! save the effective address on exceptions
        //! (interrupts) and return to the interrupted
        //! program when an rfi instruction is executed.
        SRR0,

        //! save exception status and the machine status
        //! register (MSR) on exceptions and to restore
        //! machine status register (MSR) when an rfi
        //! instruction is executed.
        SRR1,

        //! decrementing counter that provides a mechanism
        //! for causing a decrementer exception after
        //! a programmable delay.
        DEC,

        //! External Access Register
        //! controls access to the external control facility and
        //! identifies the target device for external control operations.
        EAR,

        //! Processor Identification Register
        //! differentiate between individual processors
        //! in a multiprocessor environment.
        PIR,

        //! Time Base Facility
        //! provides a long-period counter driven by
        //! an implementation-dependent frequency.
        TBU,

		TBL,

		//! MMU Control Register, specified for PowerPC440;
		MMUCR,

		//! Process ID
		PID,
    
		//! Data Exception Address Register
		DEAR,

		//! Interupt Vector Prefix Register
		IVPR,

		//! Interupt Vector Offset Register IVOR0~IVOR15
		IVOR0,
		IVOR1,
		IVOR2,
		IVOR3,
		IVOR4,
		IVOR5,
		IVOR6,
		IVOR7,
		IVOR8,
		IVOR9,
		IVOR10,
		IVOR11,
		IVOR12,
		IVOR13,
		IVOR14,
		IVOR15,

		//! Core Configuration Register
		CCR0,

		//! Exception Syndrome Register
		ESR,

		//! Debug Control Register
		DBCR0,

		//! Time Control/Status Register
		TCR,
		TSR,

		//! Total number
        NR_REG
    }Reg_Index;

	//! Spr index;
	typedef enum {
		SPR_XER = 0x001,
		SPR_LR = 0x008,
		SPR_CTR = 0x009,
		SPR_DEC = 0x016,
		SPR_SRR0 = 0x01A,
		SPR_SRR1 = 0x01B,
		SPR_PID = 0x030,
		SPR_TBRL = 0x10C,
		SPR_TBRU = 0x10D,
		SPR_TBWL = 0x11C,
		SPR_TBWU = 0x11D,
		SPR_SPRG0 = 0x110,
		SPR_SPRG1 = 0x111,
		SPR_SPRG2 = 0x112,
		SPR_SPRG3 = 0x113,
		SPR_SPRG4R = 0x104,
		SPR_SPRG5R = 0x105,
		SPR_SPRG6R = 0x106,
		SPR_SPRG7R = 0x107,
		SPR_SPRG4W = 0x114,
		SPR_SPRG5W = 0x115,
		SPR_SPRG6W = 0x116,
		SPR_SPRG7W = 0x117,
		SPR_PVR = 0x11F,
		SPR_MMUCR = 0x3B2,
		SPR_DEAR = 0x03D,
		SPR_IVPR = 0x03F,
		SPR_IVOR0 = 0x190,
		SPR_IVOR1 = 0x191,
		SPR_IVOR2 = 0x192,
		SPR_IVOR3 = 0x193,
		SPR_IVOR4 = 0x194,
		SPR_IVOR5 = 0x195,
		SPR_IVOR6 = 0x196,
		SPR_IVOR7 = 0x197,
		SPR_IVOR8 = 0x198,
		SPR_IVOR9 = 0x199,
		SPR_IVOR10 = 0x19A,
		SPR_IVOR11 = 0x19B,
		SPR_IVOR12 = 0x19C,
		SPR_IVOR13 = 0x19D,
		SPR_IVOR14 = 0x19E,
		SPR_IVOR15 = 0x19F,

		SPR_CCR0 = 0x3B3,

		SPR_ESR = 0x3E,

		SPR_DBCR0 = 0x134,

		SPR_TCR = 0x154,
		SPR_TSR = 0x150,

		NR_SPR_REG
	}SPR_Index;

} //namespace PPC
#endif  // _PPC_REGISTER_H_