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📄 regfile_adaptor.cpp

📁 浙江大学的悟空嵌入式系统模拟器
💻 CPP
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/**
 *  Copyright (c) 2005 Zhejiang University, P.R.China
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */ 

//=============================================================================
/**
 *  \file    Processor/PPC/Regfile_Adaptor.cpp
 *
 *  \brief   Regfile Interface
 *
 *  \author  Chenfeng Zhou <ini_autumn@163.com>
 *
 *  Created    : <2005-02-09 17:42:13 by Cheney Chow>
 *  Last update: <2005-02-23 13:56:07 by Cheney Chow>
 * 
 * $Id: Regfile_Adaptor.cpp,v 1.1 2005/06/16 06:01:51 qilj Exp $
 */
//=============================================================================

#include "Regfile_Adaptor.h"
#include "Utils/Debug.h"

//for PPC_ERROR();
#include "Utils/Logger.h"
#include "Reg_Utils.h"

namespace PPC {
    
    Regfile_Adaptor::Regfile_Adaptor (Core::Register_File *reg_file)
        : reg_file_ (reg_file)
    {
    }

    int Regfile_Adaptor::init ()
    {
        PPC_ASSERT(reg_file_);

        Core::Register_File::Config conf;
        
        //std::for_each (reg_info_, reg_info_ + INFO_SIZE,
		//	std::bind1st(std::ptr_fun(Regfile_Adaptor::append_info), conf));

		for (int i = 0; i < INFO_SIZE; ++i) {
			append_info(conf, reg_info_[i]);
		}

        reg_file_->configurate (conf);

		reg_file_->reset();

		init_spr_map();

        return PPC_SUCCESS;
    }

    PPC_Register& Regfile_Adaptor::operator[] (PPC_u32 index)
    {
        PPC_ASSERT ( index >= 0 && index < reg_file_->num_register() );

        return reg_file_->get_register (index);
    }

	PPC_Register& Regfile_Adaptor::get_spr (unsigned int spr_n)
	{
#ifdef PPC_DEBUG
		if (spr_map_.find((SPR_Index)spr_n) == spr_map_.end()) {
			PPC_ERROR("get_spr(): DIDN'T FIND SPR!\n");
			PPC_ASSERT(0);
		}
#endif
	
		return reg_file_->get_register(spr_map_[(SPR_Index)spr_n]);
	}

	const std::string& Regfile_Adaptor::get_spr_info(unsigned int spr_n)
	{
#ifdef PPC_DEBUG
		if (spr_map_.find((SPR_Index)spr_n) == spr_map_.end()) {
			PPC_ERROR("get_spr(): DIDN'T FIND SPR!\n");
			PPC_ASSERT(0);
		}
#endif

		return reg_info_[spr_map_[(SPR_Index)spr_n]].name;
	}

    void Regfile_Adaptor::append_info (Core::Register_File::Config& conf,
                                       const
                                       Core::Register_File::Register_Meta& info)
    {
        Core::Register_File::append_profile (conf, info.name, info.type);
    }
    
	//! This is multi-to-one map;
	void Regfile_Adaptor::init_spr_map()
	{
		spr_map_[SPR_XER] = XER;
		spr_map_[SPR_LR] = LR;
		spr_map_[SPR_CTR] = CTR;
		spr_map_[SPR_DEC] = DEC;
		spr_map_[SPR_SRR0] = SRR0;
		spr_map_[SPR_SRR1] = SRR1;
		spr_map_[SPR_PID] = PID;
		spr_map_[SPR_TBRL] = TBL;
		spr_map_[SPR_TBRU] = TBU;
		spr_map_[SPR_TBWL] = TBL;
		spr_map_[SPR_TBWU] = TBU;
		spr_map_[SPR_SPRG0] = SPRG0;
		spr_map_[SPR_SPRG1] = SPRG1;
		spr_map_[SPR_SPRG2] = SPRG2;
		spr_map_[SPR_SPRG3] = SPRG3;
		spr_map_[SPR_SPRG4R] = SPRG4;
		spr_map_[SPR_SPRG5R] = SPRG5;
		spr_map_[SPR_SPRG6R] = SPRG6;
		spr_map_[SPR_SPRG7R] = SPRG7;
		spr_map_[SPR_SPRG4W] = SPRG4;
		spr_map_[SPR_SPRG5W] = SPRG5;
		spr_map_[SPR_SPRG6W] = SPRG6;
		spr_map_[SPR_SPRG7W] = SPRG7;
		spr_map_[SPR_PVR] = PVR;
		spr_map_[SPR_MMUCR] = MMUCR;
		spr_map_[SPR_DEAR] = DEAR;
		spr_map_[SPR_IVPR] = IVPR;
		spr_map_[SPR_IVOR0] = IVOR0;
		spr_map_[SPR_IVOR1] = IVOR1;
		spr_map_[SPR_IVOR2] = IVOR2;
		spr_map_[SPR_IVOR3] = IVOR3;
		spr_map_[SPR_IVOR4] = IVOR4;
		spr_map_[SPR_IVOR5] = IVOR5;
		spr_map_[SPR_IVOR6] = IVOR6;
		spr_map_[SPR_IVOR7] = IVOR7;
		spr_map_[SPR_IVOR8] = IVOR8;
		spr_map_[SPR_IVOR9] = IVOR9;
		spr_map_[SPR_IVOR10] = IVOR10;
		spr_map_[SPR_IVOR11] = IVOR11;
		spr_map_[SPR_IVOR12] = IVOR12;
		spr_map_[SPR_IVOR13] = IVOR13;
		spr_map_[SPR_IVOR14] = IVOR14;
		spr_map_[SPR_IVOR15] = IVOR15;
		spr_map_[SPR_CCR0] = CCR0;
		spr_map_[SPR_ESR] = ESR;
		spr_map_[SPR_DBCR0] = DBCR0;
		spr_map_[SPR_TCR] = TCR;
		spr_map_[SPR_TSR] = TSR;
	}

    //! According to the sequence of Reg_Index
    Core::Register_File::Register_Meta Regfile_Adaptor::reg_info_[] =
    {
		{"GPR0", Core::Register_File::REGISTER_32BIT},
        {"GPR1", Core::Register_File::REGISTER_32BIT},
        {"GPR2", Core::Register_File::REGISTER_32BIT},
        {"GPR3", Core::Register_File::REGISTER_32BIT},
        {"GPR4", Core::Register_File::REGISTER_32BIT},
        {"GPR5", Core::Register_File::REGISTER_32BIT},
        {"GPR6", Core::Register_File::REGISTER_32BIT},
        {"GPR7", Core::Register_File::REGISTER_32BIT},
        {"GPR8", Core::Register_File::REGISTER_32BIT},
        {"GPR9", Core::Register_File::REGISTER_32BIT},
        {"GPR10", Core::Register_File::REGISTER_32BIT},
        {"GPR11", Core::Register_File::REGISTER_32BIT},
        {"GPR12", Core::Register_File::REGISTER_32BIT},
        {"GPR13", Core::Register_File::REGISTER_32BIT},
        {"GPR14", Core::Register_File::REGISTER_32BIT},
        {"GPR15", Core::Register_File::REGISTER_32BIT},
        {"GPR16", Core::Register_File::REGISTER_32BIT},
        {"GPR17", Core::Register_File::REGISTER_32BIT},
        {"GPR18", Core::Register_File::REGISTER_32BIT},
        {"GPR19", Core::Register_File::REGISTER_32BIT},
        {"GPR20", Core::Register_File::REGISTER_32BIT},
        {"GPR21", Core::Register_File::REGISTER_32BIT},
        {"GPR22", Core::Register_File::REGISTER_32BIT},
        {"GPR23", Core::Register_File::REGISTER_32BIT},
        {"GPR24", Core::Register_File::REGISTER_32BIT},
        {"GPR25", Core::Register_File::REGISTER_32BIT},
        {"GPR26", Core::Register_File::REGISTER_32BIT},
        {"GPR27", Core::Register_File::REGISTER_32BIT},
        {"GPR28", Core::Register_File::REGISTER_32BIT},
        {"GPR29", Core::Register_File::REGISTER_32BIT},
        {"GPR30", Core::Register_File::REGISTER_32BIT},
        {"GPR31", Core::Register_File::REGISTER_32BIT},

        {"FPR0", Core::Register_File::REGISTER_32BIT},
        {"FPR1", Core::Register_File::REGISTER_32BIT},
        {"FPR2", Core::Register_File::REGISTER_32BIT},
        {"FPR3", Core::Register_File::REGISTER_32BIT},
        {"FPR4", Core::Register_File::REGISTER_32BIT},
        {"FPR5", Core::Register_File::REGISTER_32BIT},
        {"FPR6", Core::Register_File::REGISTER_32BIT},
        {"FPR7", Core::Register_File::REGISTER_32BIT},
        {"FPR8", Core::Register_File::REGISTER_32BIT},
        {"FPR9", Core::Register_File::REGISTER_32BIT},
        {"FPR10", Core::Register_File::REGISTER_32BIT},
        {"FPR11", Core::Register_File::REGISTER_32BIT},
        {"FPR12", Core::Register_File::REGISTER_32BIT},
        {"FPR13", Core::Register_File::REGISTER_32BIT},
        {"FPR14", Core::Register_File::REGISTER_32BIT},
        {"FPR15", Core::Register_File::REGISTER_32BIT},
        {"FPR16", Core::Register_File::REGISTER_32BIT},
        {"FPR17", Core::Register_File::REGISTER_32BIT},
        {"FPR18", Core::Register_File::REGISTER_32BIT},
        {"FPR19", Core::Register_File::REGISTER_32BIT},
        {"FPR20", Core::Register_File::REGISTER_32BIT},
        {"FPR21", Core::Register_File::REGISTER_32BIT},
        {"FPR22", Core::Register_File::REGISTER_32BIT},
        {"FPR23", Core::Register_File::REGISTER_32BIT},
        {"FPR24", Core::Register_File::REGISTER_32BIT},
        {"FPR25", Core::Register_File::REGISTER_32BIT},
        {"FPR26", Core::Register_File::REGISTER_32BIT},
        {"FPR27", Core::Register_File::REGISTER_32BIT},
        {"FPR28", Core::Register_File::REGISTER_32BIT},
        {"FPR29", Core::Register_File::REGISTER_32BIT},
        {"FPR30", Core::Register_File::REGISTER_32BIT},
        {"FPR31", Core::Register_File::REGISTER_32BIT},

        {"CR", Core::Register_File::REGISTER_32BIT},
        {"FPSCR", Core::Register_File::REGISTER_32BIT},
        {"XER", Core::Register_File::REGISTER_32BIT},
        {"LR", Core::Register_File::REGISTER_32BIT},
        {"CTR", Core::Register_File::REGISTER_32BIT},
        {"MSR", Core::Register_File::REGISTER_32BIT},
        {"PVR", Core::Register_File::REGISTER_32BIT},
        
        {"IBATU0", Core::Register_File::REGISTER_32BIT},
		{"IBATU1", Core::Register_File::REGISTER_32BIT},
		{"IBATU2", Core::Register_File::REGISTER_32BIT},
		{"IBATU3", Core::Register_File::REGISTER_32BIT},

        {"IBATL0", Core::Register_File::REGISTER_32BIT},
		{"IBATL1", Core::Register_File::REGISTER_32BIT},
		{"IBATL2", Core::Register_File::REGISTER_32BIT},
		{"IBATL3", Core::Register_File::REGISTER_32BIT},

        {"DBATU0", Core::Register_File::REGISTER_32BIT},
		{"DBATU1", Core::Register_File::REGISTER_32BIT},
		{"DBATU2", Core::Register_File::REGISTER_32BIT},
		{"DBATU3", Core::Register_File::REGISTER_32BIT},

        {"DBATL0", Core::Register_File::REGISTER_32BIT},
		{"DBATL1", Core::Register_File::REGISTER_32BIT},
		{"DBATL2", Core::Register_File::REGISTER_32BIT},
		{"DBATL3", Core::Register_File::REGISTER_32BIT},

        {"SDR1", Core::Register_File::REGISTER_32BIT},
        {"SR", Core::Register_File::REGISTER_32BIT},
        {"DAR", Core::Register_File::REGISTER_32BIT},
        {"DSISR", Core::Register_File::REGISTER_32BIT},

        {"SPR0", Core::Register_File::REGISTER_32BIT},
        {"SPR1", Core::Register_File::REGISTER_32BIT},
        {"SPR2", Core::Register_File::REGISTER_32BIT},
        {"SPR3", Core::Register_File::REGISTER_32BIT},

		{"SPR4", Core::Register_File::REGISTER_32BIT},
		{"SPR5", Core::Register_File::REGISTER_32BIT},
		{"SPR6", Core::Register_File::REGISTER_32BIT},
		{"SPR7", Core::Register_File::REGISTER_32BIT},

        {"SRR0", Core::Register_File::REGISTER_32BIT},
        {"SRR1", Core::Register_File::REGISTER_32BIT},

        {"DEC", Core::Register_File::REGISTER_32BIT},
        {"EAR", Core::Register_File::REGISTER_32BIT},
        {"PIR", Core::Register_File::REGISTER_32BIT},

        // TBL & TBU
        {"TBU", Core::Register_File::REGISTER_32BIT},
		{"TBL", Core::Register_File::REGISTER_32BIT},

		{"MMUCR", Core::Register_File::REGISTER_32BIT},
		{"PID", Core::Register_File::REGISTER_32BIT},
		{"DEAR", Core::Register_File::REGISTER_32BIT},
		{"IVPR", Core::Register_File::REGISTER_32BIT},
		{"IVOR0", Core::Register_File::REGISTER_32BIT},
		{"IVOR1", Core::Register_File::REGISTER_32BIT},
		{"IVOR2", Core::Register_File::REGISTER_32BIT},
		{"IVOR3", Core::Register_File::REGISTER_32BIT},
		{"IVOR4", Core::Register_File::REGISTER_32BIT},
		{"IVOR5", Core::Register_File::REGISTER_32BIT},
		{"IVOR6", Core::Register_File::REGISTER_32BIT},
		{"IVOR7", Core::Register_File::REGISTER_32BIT},
		{"IVOR8", Core::Register_File::REGISTER_32BIT},
		{"IVOR9", Core::Register_File::REGISTER_32BIT},
		{"IVOR10", Core::Register_File::REGISTER_32BIT},
		{"IVOR11", Core::Register_File::REGISTER_32BIT},
		{"IVOR12", Core::Register_File::REGISTER_32BIT},
		{"IVOR13", Core::Register_File::REGISTER_32BIT},
		{"IVOR14", Core::Register_File::REGISTER_32BIT},
		{"IVOR15", Core::Register_File::REGISTER_32BIT},

		{"CCR0", Core::Register_File::REGISTER_32BIT},

		{"ESR", Core::Register_File::REGISTER_32BIT},
		{"DBCR0", Core::Register_File::REGISTER_32BIT},

		{"TCR", Core::Register_File::REGISTER_32BIT},
		{"TSR", Core::Register_File::REGISTER_32BIT}
    };

} // namespace PPC

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