mmu.h

浙江大学的悟空嵌入式系统模拟器

#ifndef _MMU_H_
#define _MMU_H_

#include <Core/Memory.h>

namespace PPC
{
	class TLB
	{
	public:
		//! TLB word 0 flag
		static const Core::u32 TLB_VALID =	0x00000200;
		static const Core::u32 TS_SET =		0x00000100;
		//! Supported page sizes 
		static const Core::u32 SZ_1K =	    0x00000000;
		static const Core::u32 SZ_4K =	    0x00000010;
		static const Core::u32 SZ_16K =	    0x00000020;
		static const Core::u32 SZ_64K =	    0x00000030;
		static const Core::u32 SZ_256K =    0x00000040;
		static const Core::u32 SZ_1M =	    0x00000050;
		static const Core::u32 SZ_16M =	    0x00000070;
		static const Core::u32 SZ_256M =    0x00000090;
		//! Storage attributes 
		static const Core::u32 SA_W =	    0x00000800;	    //!< Write-through 
		static const Core::u32 SA_I	=    0x00000400;	    //!< Caching inhibited 
		static const Core::u32 SA_M	=    0x00000200;	    //!< Memory coherence
		static const Core::u32 SA_G	=    0x00000100;	    //!< Guarded
		static const Core::u32 SA_E	=    0x00000080;	    //!< Endian
		//! Access control
		static const Core::u32 AC_X	=    0x00000024;	    //!< Execute
		static const Core::u32 AC_W	=    0x00000012;	    //!< Write
		static const Core::u32 AC_R	=    0x00000009;	    //!< Read
		//! 32-bit virtual address mapping
		static const Core::u32 CFG_SDRAM_BASE =	    0x00000000;	    //!< _must_ be 0
		static const Core::u32 CFG_FLASH_BASE =	    0xff800000;	    //!< start of FLASH
		static const Core::u32 CFG_MONITOR_BASE =    0xfff80000;	    //!< start of monitor
		static const Core::u32 CFG_PCI_MEMBASE =	    0x80000000;	    //!< mapped pci memory
		static const Core::u32 CFG_PERIPHERAL_BASE = 0xe0000000;	    //!< internal peripherals
		static const Core::u32 CFG_ISRAM_BASE =	    0xc0000000;	    //!< internal SRAM
		static const Core::u32 CFG_PCI_BASE	=    0xd0000000;	    //!< internal PCI regs

		//! TLB entry
		typedef struct 
		{
			Core::u32 ws0, ws0_TID, ws1, ws2; //!< ws0 and ws0_TID form the 40-bits word 0
		} Entry;

		//! Ctor
		TLB(size_t size);
		
		//! search for a matching tlb
		Entry * search(Core::u32 as, Core::u32 pid, Core::u32 ea, size_t * index);
	
		//! reset the tlb
		void reset();

		//! get a single entry
		Entry & get_entry(size_t index);

		//! several tlb word field extracting methods
		static Core::u32 get_EPN(Entry & entry)	{return ( entry.ws0 & 0xfffffc00 );}
		static Core::u32 get_SIZE(Entry & entry){return ( entry.ws0 & 0x000000f0 ) >> 4;}
		static Core::u32 get_V(Entry & entry){return (entry.ws0 & 0x00000200) >> 9;}
		static Core::u32 get_TS(Entry & entry) {return (entry.ws0 & 0x00000100) >> 8;}
		static Core::u32 get_RPN(Entry & entry){return ( entry.ws1 & 0xfffffc00 );}
		static Core::u32 get_ERPN(Entry & entry){return ( entry.ws1 & 0x0000000f );}
		static Core::u32 get_UX(Entry & entry){	return (entry.ws2 & 0x00000020) >> 5;}
		static Core::u32 get_UW(Entry & entry){	return (entry.ws2 & 0x00000010) >> 4;}
		static Core::u32 get_UR(Entry & entry){	return (entry.ws2 & 0x00000008 )>> 3;}
		static Core::u32 get_SX(Entry & entry){	return (entry.ws2 & 0x00000004 )>> 2;}
		static Core::u32 get_SW(Entry & entry){	return (entry.ws2 & 0x00000002 )>> 1;}
		static Core::u32 get_SR(Entry & entry){	return (entry.ws2 & 0x00000001);}

	private:
		static Entry  entrys_[66]; //!< Fix me! 
		size_t size_;
	};

	class MMU : public Core::MMU<Core::u32>
	{
	public:
		const static Core::Memory_Result ACCESS_SUCCESSFUL = 0;
		const static Core::Memory_Result ACCESS_FAULT= 1;
		const static Core::Memory_Result IO_RW = 3;

		const static Core::Memory_Access_Type DATA_READ = 0;
		const static Core::Memory_Access_Type DATA_WRITE = 1;
		const static Core::Memory_Access_Type INSTR_READ = 2; 

		//! Ctor
		MMU();

		//! Dtor
		virtual ~MMU();

		//! access memory though MMU
		virtual Core::Memory_Result access(Core::Memory_Access_Type type, 
			Core::u32 start, size_t size, Core::Bytecode_Type & buffer);

		//! get the unified tlb 
		TLB & get_utlb();

	private:
		TLB * utlb_;
	};

} // namespace PPC

#endif // _MMU_H_